Senior Design Verification Engineer

HCLTech; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Competitive salary

Professional development opportunities

Dynamic work environment

Job summary

HCLTech is seeking a talented Design Verification Engineer in Bengaluru, India, to ensure the functionality and quality of integrated circuits. Candidates should possess 6-10 years of relevant experience, a Bachelor's degree in Engineering, and proficiency in verification methodologies and tools like Verilog.

This role offers competitive salary and benefits, opportunities for professional development, and a collaborative work environment focused on cutting-edge technologies.

Qualifications

• 6-10 years of experience in design verification for ASICs or SoCs.
• Strong understanding of digital design principles.
• Proven ability to develop and debug complex verification environments.

Responsibilities

• Develop and implement comprehensive verification plans.
• Design and write verification environments to achieve high code coverage.
• Utilize simulation tools to verify RTL functionality.

Skills

Verification methodologies

RTL design

Verilog

VHDL

Simulation tools

Python

Problem-solving skills

Communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree (preferred)

Tools

ModelSim

Cadence Incisive

Synopsys VCS

Job description

We are looking for a talented and motivated Design Verification Engineer with minimum 6 yrs of relevant experience to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools

Responsibilities

• s: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., U
• VM)Design and write robust verification environments (testbenches) to achieve high code cover
• ageUtilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functional
• ityDebug and analyze verification failures to identify the root cause of design iss
• uesCollaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requireme
• ntsParticipate in code reviews and ensure adherence to verification coding standa
• rdsStay up-to-date with the latest verification tools and methodolog

Qualifications

• ons: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a
• plus)6-10 years of experience in design verification for ASICs or
• SoCsStrong understanding of digital design principles (combinational logic, sequential l
• ogic)Proven ability to develop and debug complex verification environ
• mentsProficiency in Verilog or VHDL with experience in verification methodologies (e.g.,
• UVM)Experience with simulation tools and scripting languages (e.g., Python, Perl) is a
• plusExcellent analytical and problem-solving s
• killsStrong communication and collaboration skills to work effectively in a team enviro
• efits:Competitive salary and benefits p
• ackageOpportunity to work on leading-edge technologies and pr
• ojectsCollaborative and dynamic work envir
• onmentPotential for professional development and career advan