Senior Engineer - DV

Quest Global; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Quest Global in Hyderabad is looking for a Senior Design Verification Engineer with at least 4 years of experience in ASIC/SoC Design Verification. The role requires strong expertise in SystemVerilog and UVM, alongside experience in developing UVM testbenches and performing verification activities. Candidates should also be familiar with debugging RTL and testbench issues and collaborating with design and architecture teams. Join us to make an impact in a dynamic environment.

Qualifications

• Minimum 4 years of experience in ASIC/SoC Design Verification.
• Strong hands-on experience with SystemVerilog and UVM.
• Good understanding of AMBA protocols (AXI / AHB / APB) is a plus.

Responsibilities

• Develop and maintain UVM testbenches, sequences, drivers, monitors, and scoreboards.
• Perform block-level and subsystem-level verification.
• Collaborate with design, validation, and architecture teams.

Skills

SystemVerilog

UVM

Functional Verification

Coverage-driven Verification

Debug & Root Cause Analysis

Tools

Git

Perforce

Job description

Job Requirements

Senior Design Verification Engineer | 4 Years Experience

4 years of experience in ASIC/SoC Design Verification

Strong hands-on experience with SystemVerilog and UVM

Developed and maintained UVM testbenches, sequences, drivers, monitors, and scoreboards

Performed block-level and subsystem-level verification

Experienced in test plan creation, coverage analysis (functional & code coverage), and closure

Worked on debugging RTL and testbench issues using simulators (VCS / Questa / Xcelium)

Good understanding of AMBA protocols (AXI / AHB / APB) (if applicable)

Experience in regression runs, bug tracking, and verification sign‑off

Collaborated closely with design, validation, and architecture teams

Familiar with version control (Git/Perforce) and CI/regression flows

Mentored junior engineers and supported reviews

Work Experience

Key Skills

• SystemVerilog, UVM
• Functional Verification
• Coverage-driven Verification
• Debug & Root Cause Analysis
• ASIC / SoC Verification Flo