Senior Design Engineer

HCLTech; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Benefits offered by this job

Competitive compensation

Career advancement

Mentorship

Dynamic work environment

Job summary

HCLTech in Bengaluru seeks an experienced Design Verification engineer to develop verification plans for ASICs/SoCs using UVM and Formal methods. You will design high‑quality testbenches, drive code coverage, and verify RTL functionality with simulators.

Lead and mentor junior DV engineers, participate in code reviews, and keep up to date with the latest verification tools. Proficiency in Verilog or VHDL, Python/Perl, and experience with ModelSim, Cadence Incisive or Synopsys VCS are required.

Qualifications

• 7–10 years of solid experience in Design Verification for ASICs or SoCs.
• In‑depth knowledge of digital design principles (combinational, sequential, FSM).
• Proven ability to develop, debug, and optimize complex verification environments.
• Expertise in Verilog or VHDL with UVM and Formal verification methodologies.
• Extensive experience with simulation tools and scripting languages.
• Strong communication, collaboration, and leadership skills.

Responsibilities

• Develop and implement verification plans using industry methods (UVM, Formal).
• Design testbenches to achieve high code coverage.
• Verify RTL functionality with simulators and formal tools.
• Debug verification failures and identify root causes of design issues.
• Collaborate with RTL designers to ensure verification adherence.
• Lead and mentor junior DV engineers within the team.
• Participate in code reviews and promote best practices for verification code quality.
• Stay updated with latest verification tools and methodologies.

Skills

Leadership

Teamwork

Analytical thinking

Problem solving

Education

Bachelor's degree in Electrical/Computer Engineering

Master’s degree preferred

Tools

Verilog

VHDL

ModelSim

Cadence Incisive

Synopsys VCS

Python

Perl

Job description

Responsibilities

• Develop and implement comprehensive verification plans utilizing industry‑leading methodologies (UVM, Formal Verification).
• Design and create high‑quality verification environments (testbenches) to achieve exceptional code coverage.
• Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality.
• Debug and analyze verification failures to identify and resolve the root cause of design issues.
• Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence.
• Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge‑sharing environment.
• Participate in code reviews and champion best practices for verification code quality.
• Stay current with the latest advancements in verification tools and methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s degree a plus).
• 7-10 years of solid experience in Design Verification for ASICs or SoCs.
• In‑depth knowledge of digital design principles (combinational logic, sequential logic, finite state machine).
• Proven ability to develop, debug, and optimize complex verification environments.
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal).
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl).
• Experience with formal verification tools and techniques is a plus.
• Excellent analytical and problem‑solving skills with meticulous attention to detail.
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team.

Benefits

• Competitive salary and benefits package commensurate with experience.
• Opportunity to work on leading‑edge technologies and projects with a high impact.
• Collaborative and dynamic work environment that fosters continuous learning.
• Potential for professional development and career advancement.