Design Verification Engineer

Proxelera; Hyderabad; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

A leading semiconductor company in Hyderabad is looking for a Senior Talent Acquisition Specialist focused on VLSI and Semiconductor hiring. The role involves overseeing IP-level functional verification, developing testbenches, and ensuring high-quality IP delivery within project timelines. Candidates should have 3–5 years of relevant experience, with a strong background in digital design fundamentals and experience using UVM. This full-time position offers great opportunities for growth in the semiconductor sector.

Qualifications

• 3–5 years of experience in talent acquisition in the semiconductor industry.
• Hands-on experience with IP-level verification methodologies.
• Strong understanding of digital design fundamentals.
• Understanding of AXI/AHB/Ethernet interfaces for IP verification.
• Scripting skills (Python, Perl, Shell) to automate verification tasks.

Responsibilities

• Oversee IP-level functional verification and testbench development.
• Debug functional issues and analyze waveforms/logs.
• Ensure quality IP delivery within project timelines.
• Apply industry verification methodologies and digital design fundamentals.
• Support verification automation and regression using scripting.

Skills

Functional verification using UVM

IP-level functional verification

SystemVerilog

Debugging

Scripting languages (Python, Perl, Shell)

RTL verification

debugging

waveforms/logs analysis

digital design fundamentals

AXI/AHB/Ethernet protocols

Python/Perl/Shell scripting

Tools

SystemVerilog

UVM

AXI

AHB

Ethernet

Job description

Senior Talent Acquisition Specialist | VLSI | Semiconductor | Embedded Hiring

Experience: 3–5 Years

Hiring Design Verification Engineer with strong IP-level / Functional Verification experience using UVM to support high-quality IP development programs. If you enjoy solving real-world verification problems and contributing to high-quality IP delivery, this role offers an excellent opportunity to grow and make an impact.

Job Description:

• Hands‑on experience in IP-level functional verification using SystemVerilog and UVM, including testbench development and test case creation.
• Perform RTL verification, debug functional issues, analyze waveforms/logs, and ensure quality IP delivery within project timelines.
• Solid understanding of digital design fundamentals and industry-standard verification methodologies.
• Exposure to on‑chip bus and interface protocols such as AXI, AHB, and Ethernet for IP verification.
• Utilize scripting languages (Python, Perl, Shell) to support verification automation, regression, and productivity improvements.

Seniority level

Mid-Senior level

Employment type

Full‑time

Job function

Design

Industries

Semiconductor Manufacturing