Senior Design Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks a Senior Design Verification Engineer to own verification of UCIe-based chiplet designs with FDI/RDI interfaces and protocol behavior. You will develop scalable SystemVerilog/UVM testbenches, checkers, and coverage, verify PCIe/CXL over UCIe, and drive coverage-driven verification while collaborating with RTL, architecture, and firmware teams.

The role requires 6–10 years of hands-on experience, strong debugging skills, and the ability to work

Qualifications

• 6–10 years of hands-on Design Verification experience.
• Strong SystemVerilog, UVM, SVA and verification methodology expertise.
• Deep understanding of UCIe – FDI/RDI, chiplet architectures, and die-to-die communication.
• Hands-on experience with PCIe and/or CXL, preferably deployed over UCIe.
• Strong protocol-level debugging and coverage-closure skills.
• Experience with industry-standard simulation and debug tools.

Responsibilities

• Own verification of UCIe-based chiplet designs, covering FDI/RDI interfaces and protocol/data-path behavior.
• Develop scalable SystemVerilog/UVM testbenches, test plans, checkers, scoreboards, assertions, and functional coverage.
• Verify PCIe/CXL over UCIe, including protocol transactions, error handling, link behavior, and interoperability scenarios.
• Drive constrained-random, directed, assertion-based, and coverage-driven verification.
• Debug complex RTL/protocol issues across simulation, regressions, and waveform analysis.
• Collaborate closely with RTL, architecture, firmware, and post-silicon teams to close verification gaps.

Skills

SystemVerilog

UVM

SVA

UCIe – FDI/RDI

PCIe/CXL

Python scripting

Debugging

Job description

We are looking for a Senior Design Verification Engineer with strong expertise in UCIe, Chiplet architectures, PCIe/CXL protocols, and end-to-end SoC/IP verification.

Key Responsibilities

• Own verification of UCIe-based chiplet designs, covering FDI/RDI interfaces and protocol/data-path behavior.
• Develop scalable SystemVerilog/UVM testbenches, test plans, checkers, scoreboards, assertions, and functional coverage.
• Verify PCIe/CXL over UCIe, including protocol transactions, error handling, link behavior, and interoperability scenarios.
• Drive constrained-random, directed, assertion-based, and coverage-driven verification.
• Debug complex RTL/protocol issues across simulation, regressions, and waveform analysis.
• Collaborate closely with RTL, architecture, firmware, and post-silicon teams to close verification gaps.

Required Skills

• 6–10 years of hands-on Design Verification experience.
• Strong SystemVerilog, UVM, SVA, and verification methodology expertise.
• Deep understanding of UCIe – FDI/RDI, chiplet architectures, and die-to-die communication.
• Hands-on experience with PCIe and/or CXL, preferably deployed over UCIe.
• Strong protocol-level debugging and coverage closure skills.
• Experience with industry-standard simulation and debug tools.

Good to Have

• UCIe compliance/interoperability or multi-die SoC verification experience.
• Experience with PCIe/CXL protocol checkers, VIPs, and formal verification.
• Strong Python/Perl/Tcl scripting for verification automation.