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Scaledge is seeking an experienced Senior Design Verification Engineer to verify complex SoC/ASIC designs with SystemVerilog and UVM. You will implement advanced testbenches, coverage-driven verification, and robust assertions, focusing on high-speed interfaces like PCIe, USB, DDR, Ethernet, and AXI.
You will collaborate with RTL, software, and QA teams to ensure high quality silicon, mentor junior engineers, and drive verification milestones in a fast-paced environment.
We are looking for an experienced Senior Design Verification Engineer with 4+ years of hands-on experience in SoC/ASIC Design Verification. The ideal candidate should have strong expertise in SystemVerilog, UVM, functional coverage, assertions, and high-speed interface protocols
Strong experience in System Verilog and UVM methodology
Hands-on expertise in high-speed interface protocols (PCIe / USB / DDR / Ethernet / AXI, etc.)
Good understanding of verification concepts, coverage, assertions, and debugging
Experience with simulation tools (VCS, Questa, Xcelium, etc.
Strong analytical & problem-solving skillsRole & responsibilities