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Sevya Multimedia in Hyderabad is seeking experienced engineers to verify an IP/full-chip using SystemVerilog and UVM. The role emphasizes PCIe/DDR verification at IP/SoC level, along with robust constrained-random verification, test plans, and coverage-driven debugging.
The candidate will work with leading EDA tools and scripting in Shell/Python, contribute to verification methodologies, and collaborate within a global team to deliver high-quality designs on schedule.
We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level.