IP/SOC Design Verification Engineer

Tessolve; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Tessolve in Bengaluru seeks experienced IP/SoC Verification Engineers to join our expanding team. The role focuses on building verification environments, developing test plans, running simulations, and collaborating with design and architecture to ensure first-pass silicon success.

Ideal candidates will have strong SystemVerilog and UVM skills and a track record verifying PCIe, DDR, USB, and Ethernet protocols. You will mentor juniors and contribute to verification methodology improvements.

Qualifications

• 5–15 years of IP/SoC Verification.
• Strong proficiency in SystemVerilog and UVM.
• Experience in verification of one or more protocols: DDR (DDR4/DDR5/LPDDR), USB (USB 2.0/3.x), Ethernet (1G/10G/25G/100G).
• Good understanding of verification methodologies, assertions (SVA), and coverage-driven verification.
• Experience with industry-standard simulators such as VCS, Xcelium, or Questa.

Responsibilities

• Develop and execute comprehensive verification plans for IP and SoC-level designs.
• Build scalable and reusable UVM-based verification environments.
• Develop test cases, sequences, scoreboards, monitors, and coverage models.
• Verify complex protocols including PCIe, DDR, USB, and Ethernet.
• Perform functional, code, assertion, and toggle coverage analysis and closure.
• Debug RTL, testbench, and simulation issues to identify root causes.
• Work closely with design, architecture, firmware, and validation teams throughout the project lifecycle.
• Drive verification sign-off and ensure quality deliverables within project timelines.
• Mentor junior engineers and contribute to verification methodology improvements.

Skills

SystemVerilog

UVM

IP/SoC Verification

PCIe

DDR

USB

Ethernet

SVA

Python

Tools

VCS

Xcelium

Questa

Job description

Experience: 5–25 Years

About the Role

We are looking for experienced IP/SoC Verification Engineers to join our growing verification team. The ideal candidate will have strong expertise in SystemVerilog, UVM, and verification of high-speed protocols such as PCIe, DDR, USB, and Ethernet. The role involves developing verification environments, creating test plans, executing simulations, and collaborating closely with design and architecture teams to ensure first-pass silicon success.

Key Responsibilities

• Develop and execute comprehensive verification plans for IP and SoC-level designs.
• Build scalable and reusable UVM-based verification environments.
• Develop test cases, sequences, scoreboards, monitors, and coverage models.
• Verify complex protocols including PCIe, DDR, USB, and Ethernet.
• Perform functional, code, assertion, and toggle coverage analysis and closure.
• Debug RTL, testbench, and simulation issues to identify root causes.
• Work closely with design, architecture, firmware, and validation teams throughout the project lifecycle.
• Drive verification sign-off and ensure quality deliverables within project timelines.
• Mentor junior engineers and contribute to verification methodology improvements.

Required Skills

• 5–15 years of experience in IP/SoC Verification.
• Strong proficiency in SystemVerilog and UVM.
• Experience in verification of one or more protocols:
• DDR (DDR4/DDR5/LPDDR)
• USB (USB 2.0/3.x)
• Ethernet (1G/10G/25G/100G)
• Good understanding of verification methodologies, assertions (SVA), and coverage-driven verification.
• Experience with industry-standard simulators such as VCS, Xcelium, or Questa.
• Strong debugging and problem-solving skills.
• Knowledge of scripting languages such as Python, Perl, Tcl, or Shell scripting.

Preferred Qualifications

• Experience in SoC-level verification and subsystem integration.
• Exposure to ARM-based SoCs, interconnects, DMA, memory controllers, and cache coherency protocols.
• Experience with Formal Verification, Emulation, or FPGA prototyping is an added advantage.
• Strong communication and collaboration skills.