IP Design Verification Director

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies is seeking a seasoned Director of Design Verification to lead verification for a flagship SoC portfolio. You will define the verification strategy, oversee execution, and ensure first-pass silicon success for server, storage, and networking domains.

This hands-on leadership role requires 20+ years in design verification, deep PCIe/CXL expertise, and a track record of mentoring teams, developing UVM test plans, and using AI-augmented flows to accelerate coverage closure.

Qualifications

• 20+ years in design verification
• Led teams and delivered complex SoC/silicon products
• Strong PCIe/CXL protocol expertise (Gen3+)
• Experience with UVM-based test plans and coverage analysis
• Knowledge of AI-augmented verification flows

Responsibilities

• Own and drive end-to-end verification methodology for a product line
• Mentor and grow verification team
• Guide PCIe and CXL verification across physical, link, and transaction layers
• Collaborate with RTL, architecture, and software teams
• Represent verification in executive reviews and customer engagements

Skills

UVM

Formal verification

PCIe

CXL

VIP (Verification IPs)

Test plan development

Assertions

Coverage analysis

Leadership

AI-driven verification

Education

Bachelor's in Electrical or Computer Engineering

Master's preferred

Tools

Verification IPs (PCIe/CXL)

Job description

Top30 Semiconductor Organization in the world

Overview

We are seeking a seasoned Director of Design Verification with 20+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.

Key Responsibilities

• Own and drive the end-to-end verification methodology for a specific product line.Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.
• Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.
• Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.
• Represent verification in executive reviews, customer engagements, and industry forums.
• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.
• Bachelor’s degree in Electrical or Computer Engineering (Master’s prefer
• red).
• 20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party VerificationIPs.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.
• Required Experience
• Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage
• data.
• Experience in developing VIP abstraction layers to simplify and scale verification deployments.
• Preferred Experience
• Expertise in verifying PCIe / CXL Physical, Link, and Transaction layers, including compliance for EP/RC.
• Experience with buffering, queuing, and QoS in complex NoC-based SoCs.System-level performance analysis on switching fabrics.
• Familiarity with AI-driven verification methodologies and workforce transformation strategies.