RTL Synthesis and STA

Acesoft Labs; Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Acesoft Labs in India seeks a STA & Synthesis Engineer with 3–7 years of hands-on RTL synthesis experience. You will optimize designs for performance, power, and area, implement DFT insertions (MBIST/SCAN) and set up timing constraints for functional and test modes.

You will collaborate with RTL design and PD teams to release RTL to netlist, resolve timing issues, and drive timing convergence using Genus/Tempus/Innovus and Design Compiler. WFO Hyderabad/Bangalore.

Qualifications

• Proven hands-on experience on Design Compiler/Genus/Fusion Compiler.
• Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team.
• Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration.
• Ability to work with RTL design team to identify the must changes in RTL to converge the timing and work with PD teams to analyze the post route timing and support the final timing closure.
• Hands-on experience constraint development for synthesis from scratch is a plus.
• Excellent problem-solving skills.
• Team player with great interpersonal communication skills.

Responsibilities

• Perform RTL Synthesis to optimize for Performance/Power/Area.
• Implement DFT insertions including MBIST and SCAN and set up timing constraints for functional and test modes.
• Drive timing convergence for complex blocks and release netlists to PD team.
• Collaborate with RTL design and PD teams to identify RTL changes to meet timing goals.
• Develop constraints for synthesis from scratch when needed.

Skills

RTL Synthesis

Timing Analysis

DFT/MBIST/SCAN

Constraint Development

Teamwork

Problem-Solving

Tools

Genus

Tempus

Innovus

Design Compiler

Fusion Compiler

Job description

Dear Candidate,

We are hiring for our esteemed client for the role STA & Synthesis Engineer.

Exp - 3+ Years

NP - Immediate to 15 Days

Location - Bangalore, Hyd (WFO)

JD -

Synthesis & STA Engineers:

Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.

• Proven hands-on experience on Design compiler/Genus/Fusioncompiler
• Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team
• Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration.
• Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD teams to analyze the post route timing and support the final timing closure.
• Hands-on experience constraint development for synthesis from scratch is a plus
• Excellent problem-solving skills.
• Team player with great interpersonal communication skills.
• Experience: 3-7 years
• Tools: Genus/Tempus/Innovus

Based out of Hyderabad/Bangalore location.

With Regards,

Swantana