STA (Static Timing Analysis) and Synthesis Engineer

7Rays Semiconductors; Bengaluru; Sur place; INR 900 000 - 1 300 000; Plein temps

Résumé du poste

7Rays Semiconductors, Bangalore/Noida based, is seeking a STA/Synthesis Engineer to drive timing closure for SoC designs. The role requires 5+ years of hands-on STA/Synthesis experience, expertise in TCL scripting and UNIX, and leadership of a small team.

You will work with RTL, PD, and HMs teams to deliver reliable post-silicon performance and meet sign-off goals. Strong communication skills and a collaborative mindset are essential to coordinate cross-functional activities across multiple

Qualifications

• 5+ years experience in STA/Synthesis.
• Hands-on knowledge of Synthesis and Static Timing Analysis.
• Experience with Prelayout timing analysis and post-layout timing reports.
• Familiarity with RTL, PD, and HM teams for SoC timing closure.

Responsabilités

• Lead the STA/Synthesis team of 4–5 members.
• Perform timing closure across corners and modes for SoC designs.
• Prepare ECOs to fix timing violations and DRCs.
• Collaborate with RTL design, PD teams and HMs to achieve sign-off goals.

Connaissances

STA/Synthesis

Synthesis

Static Timing Analysis

Team leadership

TCL scripting

UNIX

Timing closure

Description du poste

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job: STA/Synthesis Engineer

Location- Bangalore and Noida

• 5+ years experience in STA/Synthesis
• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.
• USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Good Knowledge of TCL scripting and UNIX env.
• Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
• Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapaout timing closure skills across corners and modes.
• Must have worked with RTL design team, PD team and HMs team for overall timing closure for SoC.