ASIC Engineer 2

Acesoft Labs; Hyderabad; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Acesoft Labs in Hyderabad is seeking Synthesis & STA Engineers to optimize RTL implementations and drive timing closure across complex blocks. You will apply MBIST/SCAN DFT techniques, set timing constraints for functional and test modes, and validate netlist readiness for the PD team.

Experience of 3–7 years with Genus/Tempus/Innovus is preferred, and collaboration with RTL and PD teams is essential for successful releases from RTL to netlist.

Qualifications

• Hands-on experience with RTL synthesis tools such as Design Compiler, Genus, Fusion Compiler.
• Experience timing analysis and timing convergence for complex blocks and release netlists to PD team.
• Ability to own and release complex blocks from RTL to netlist with timing QOR and DFT constraint integration.

Responsibilities

• Perform RTL Synthesis and DFT insertions (MBIST/SCAN) to optimize Performance/ Power/ Area.
• Set up timing constraints for functional and test modes and validate results.
• Collaborate with RTL and PD teams to achieve timing closure for complex blocks.

Skills

RTL Synthesis

Timing analysis

DFT constraints

Constraint development

Team collaboration

Tools

Genus

Tempus

Innovus

Job description

• Synthesis & STA Engineers:
• Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/ Power/ Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.
• Proven hands-on experience on Design compiler/ Genus/ Fusioncompiler
• Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team
• Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration.
• Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD teams to analyze the post route timing and support the final timing closure.
• Hands-on experience constraint development for synthesis from scratch is a plus
• Excellent problem-solving skills.
• Team player with great interpersonal communication skills.

Experience : 3-7 years

Tools : Genus/Tempus/Innovus

• Based out of Hyderabad/Bangalore location