RTL Engineer/ RTL Lead and above

Tessolve; Bengaluru; Remote; INR 1,000,000 - 1,500,000; Full time

Job summary

A semiconductor company in Bangalore is seeking experienced RTL ASIC engineers with 5+ years of experience in RTL design and ASIC development. Candidates should be skilled in tools such as Lint and CDC, and have knowledge of AMBA protocols. This role covers tasks such as SOC verification and third-party VIP integration. Interested candidates can apply via email.

Qualifications

• Minimum 5 years of experience in RTL/ASIC/IP Design.
• Experience with ASIC development tools required.
• Understanding timing concepts is essential.
• Knowledge of AMBA protocols is beneficial.

Responsibilities

• SOC Verification using C/SV.
• Integrate Third Party VIP.
• Work with High Speed Serial Interfaces like PCIe or USB.
• Conduct Coverage Closure for Code, Functional and Toggle.
• Document Testbench Specifications and Test Plans.

Skills

RTL ASIC

CDC

Lint

Synthesis

Spyglass

Tools

Synopsys VCS

Cadence Incisive

Job description

Overview

Opportunity with Tessolve Semiconductor - Bangalore

We are hiring RTL design engineer and design verification engineer for Bangalore location. Experience: 5+ years. Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass. We are hiring for RTL ASIC engineer. 7+ years work experience in ASIC/IP Design. Experience in Logic design / RTL design. IP design and integration. Experience in using tools in ASIC development such as Lint and CDC are a must. Experience in Synthesis / Understanding of timing concepts is a plus. Good to have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Location: PAN INDIA.

Responsibilities

• SOC Verification using C/SV
• Third Party VIP Integration
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI
• Coverage Closure: Code, Functional and Toggle
• Tools: Synopsys VCS or Cadence Incsive
• Technical Documentation: Testbench Specification, Test Plan Specification
• Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Qualifications

• 5 to 20 years of experience in RTL/ASIC/IP Design
• Experience with ASIC development tools such as Lint, CDC, Synthesis
• Understanding of timing concepts
• Knowledge of AMBA protocols (AXI, AHB, APB) and SoC clocking/reset
• Location: PAN India

Apply

Interested candidates, please share updated CV to [e-mail] or connect on 6361542656.