Sr. Design Engineer 1

Tessolve; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Tessolve is seeking a Senior Synthesis & Static Timing Analysis Engineer in Bangalore. You will lead RTL-to-netlist implementation, collaborating with diverse teams to deliver sign-off quality results for complex SoC/ASIC designs, using Synopsys and Cadence tools.

The role emphasizes driving timing closure, crafting timing constraints, and optimizing flows across synthesis and STA within Tessolve’s embedded engineering teams.

Qualifications

• Bachelor's or Master's in Electronics, Electrical or VLSI Engineering.
• Proficient with Synopsys and Cadence for synthesis and STA.
• Proficient in TCL/Perl/Python scripting.
• Experience with advanced process nodes (7nm/5nm/3nm).

Responsibilities

• Perform RTL synthesis using Synopsys and Cadence, optimizing for PPA.
• Develop and maintain timing constraints for synthesis and STA.
• Execute Static Timing Analysis at block and top levels.
• Analyze and resolve timing violations and perform ECOs.
• Collaborate with design teams to achieve timing closure and sign-off.
• Enhance flow methodologies across synthesis and STA stages.

Skills

RTL synthesis

Static Timing Analysis

TCL scripting

Perl scripting

Python scripting

Synopsys Cadence tools

Process node awareness

Collaboration

Education

B.E./B.Tech in Electronics or Electrical or VLSI Engineering

Tools

Synopsys tools

Cadence tools

Job description

About Us

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve’s design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve’s Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolve’s clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

For more details, visit https://www.tessolve.com/

Job Overview

Join our innovative team as a Senior Synthesis & Static Timing Analysis Engineer, where you will lead the RTL-to-netlist implementation flow. Collaborate with diverse teams to deliver sign-off quality results for complex SoC/ASIC designs, leveraging advanced tools like Synopsys and Cadence. Your contributions will significantly impact our embedded engineering services in sectors such as automotive, industrial, and medical, all from our world-class facilities.

Job Designation: Senior Synthesis & Static Timing Analysis Engineer

Job Location : Bangalore

What you'll do

• Perform RTL synthesis using Synopsys and Cadence, optimizing for PPA.
• Develop and maintain timing constraints for synthesis and STA.
• Execute Static Timing Analysis at both block and top levels.
• Analyze and resolve timing violations and perform necessary ECOs.
• Collaborate with design teams to achieve timing closure and sign-off.
• Enhance flow methodologies across synthesis and STA stages.

Who you are

• Holder of a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering.
• Proficient with Synopsys and Cadence tools for synthesis and STA.
• Skilled in scripting with TCL, Perl, and Python.
• Experienced with advanced process nodes (7nm/5nm/3nm).
• Strong analytical and collaborative skills for global teamwork.

Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries (“Tessolve”) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at [e-mail]. Tessolve is not responsible for any losses incurred due to such fraudulent activities