RTL Engineer

SKaaS- Skills as a Service; Bengaluru; Sur place; INR 1 800 000 - 2 600 000; Plein temps

Résumé du poste

SKaaS- Skills as a Service in Bengaluru seeks an experienced ASIC/SoC RTL Design engineer with 5+ years in the field and 2+ years focused on CPU core RTL work. Solid with SystemVerilog/Verilog/VHDL and AMBA protocols, you will contribute to core design and verification efforts.

Required proficiency with front-end tools and scripting, plus familiarity with post-silicon bring-up. This role targets candidates who can work on complex processor subsystems in a fast-paced environment.

Qualifications

• 5+ years total experience in ASIC/SoC RTL Design.
• At least 2+ years dedicated to CPU core or processor subsystem RTL design.
• Proficient in SystemVerilog, Verilog, and VHDL.
• Understanding of instruction pipelines, hazards, and caches.
• Experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Hands-on with SpyGlass, VCS, DC, or Genus/Xcelium.
• Python, Perl, TCL, or Bash scripting for automation.
• Exposure to FPGA prototyping or post-silicon bring-up and debug.
• Familiarity with assembly programming (RISC-V/ARM) for diagnostics.

Connaissances

SystemVerilog

Verilog

VHDL

CPU core RTL

RTL design

RISC-V familiarity

ARM/x86 familiarity

Pipelines & hazards

AMBA protocols

Debug bring-up

Python scripting

Formation

B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering

Outils

SpyGlass

VCS

Design Compiler (DC)

Genus/Xcelium

Description du poste

Education: B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering.

Experience: 5+ total years in ASIC/SoC RTL Design, with at least 2+ years dedicated to CPU core or processor subsystem RTL design (RISC-V, ARM, x86, or proprietary cores).

• Hardware Description Languages: Proficient in SystemVerilog, Verilog, and VHDL.
• CPU Microarchitecture Knowledge: Understanding of computer organization— instruction execution pipelines, hazard handling, branch prediction, L1/L2 caches, memory management units (MMU), and interrupts.
• Bus Protocols: Hands-on experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Front-End Tools: Hands-on experience with Synopsys SpyGlass (Lint/CDC), VCS, Design Compiler (DC), or Cadence Genus/Xcelium.
• Scripting: Python, Perl, TCL, or Bash for automation. Preferred Qualifications
• Exposure to FPGA prototyping or post-silicon bring-up and debug.
• Familiarity with assembly programming (RISC-V/ARM) for basic diagnostic bring-up tests.