RTL Design Engineer – CPU & Microarchitecture

SKaaS- Skills as a Service; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

SKaaS- Skills as a Service in Bengaluru invites an experienced RTL Design Engineer to contribute to ASIC/SoC projects. You should have 5+ years in RTL design, with at least 2+ years on CPU cores (RISC-V/ARM/x86).

Proficiency in SystemVerilog, Verilog, and VHDL is required along with hands-on experience with AMBA protocols and front-end tooling (SpyGlass, VCS, DC, Genus/Xcelium). Scripting skills (Python/Perl/TCL/Bash) are a plus.

Qualifications

• 5+ years total ASIC/SoC RTL Design experience.
• At least 2+ years in CPU core or processor subsystem RTL design (RISC-V, ARM, x86 or proprietary cores).
• Proficient in SystemVerilog, Verilog, and VHDL.
• Strong understanding of AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Experience with front-end tools: SpyGlass, VCS, Design Compiler, Genus or Xcelium.
• Scripting skills in Python, Perl, TCL, or Bash.

Skills

SystemVerilog

Verilog

VHDL

CPU architecture knowledge

AMBA protocols

Scripting

Education

B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering

Tools

SpyGlass

VCS

Design Compiler

Genus

Xcelium

Job description

Education: B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering.

Experience: 5+ total years in ASIC/SoC RTL Design, with at least 2+ years dedicated to CPU core or processor subsystem RTL design (RISC-V, ARM, x86, or proprietary cores).

• Hardware Description Languages: Proficient in SystemVerilog, Verilog, and VHDL.
• CPU Microarchitecture Knowledge: Understanding of computer organization— instruction execution pipelines, hazard handling, branch prediction, L1/L2 caches, memory management units (MMU), and interrupts.
• Bus Protocols: Hands-on experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Front-End Tools: Hands-on experience with Synopsys SpyGlass (Lint/CDC), VCS, Design Compiler (DC), or Cadence Genus/Xcelium.
• Scripting: Python, Perl, TCL, or Bash for automation.

Preferred Qualifications

• Exposure to FPGA prototyping or post-silicon bring-up and debug.
• Familiarity with assembly programming (RISC-V/ARM) for basic diagnostic bring-up tests.