CPU RTL Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking a CPU RTL Design Engineer to design, implement, and optimize high-performance CPU cores for next-generation ARM and RISC-V processors. The role focuses on translating microarchitectural specs into synthesizable RTL and improving pipelines, caches, and memory subsystems.

Ideal candidates have 5–10 years of CPU RTL/Processor Design experience, strong Verilog/SystemVerilog skills, and a deep understanding of CPU architectures, pipelines, and performance

Qualifications

• 5–10 years of experience in CPU RTL Design / Processor Design.
• Hands-on expertise in Verilog / SystemVerilog RTL design.
• Experience with ARM processor architecture and/or RISC-V ISA.
• Strong understanding of CPU Microarchitecture and Computer Architecture.
• Experience with RTL simulation, debugging, and synthesis-aware coding practices.

Responsibilities

• Develop and implement CPU RTL designs based on microarchitectural specifications.
• Work on CPU pipelines, instruction execution, branch prediction, load/store units, and memory subsystems.
• Translate microarchitecture and computer architecture concepts into synthesizable RTL.
• Design and optimize CPU datapaths, control logic, and performance-critical blocks.
• Collaborate with architecture, verification, physical design, and performance teams.
• Debug RTL issues, perform functional analysis, and support design quality and signoff.

Skills

CPU RTL Design

Processor Design

CPU Microarchitecture

Computer Architecture

RTL Debugging

Performance Optimization

Collaboration

Problem Solving

Synthesis-aware coding

Tools

Verilog

SystemVerilog

Job description

We are looking for a CPU RTL Design Engineer with strong expertise in CPU microarchitecture, computer architecture, and RTL development for next-generation ARM and RISC-V processors. The ideal candidate will contribute to designing, implementing, and optimizing high-performance CPU cores.

Key Responsibilities:

• Develop and implement CPU RTL designs based on microarchitectural specifications.
• Work on CPU pipelines, instruction execution, branch prediction, load/store units, and memory subsystems.
• Translate microarchitecture and computer architecture concepts into synthesizable RTL.
• Design and optimize CPU datapaths, control logic, and performance-critical blocks.
• Collaborate with architecture, verification, physical design, and performance teams.
• Debug RTL issues, perform functional analysis, and support design quality and signoff.

Core Technical Requirements:

• 5-10 years of experience in CPU RTL Design / Processor Design.
• Strong understanding of CPU Microarchitecture and Computer Architecture.
• Hands-on expertise in Verilog / SystemVerilog RTL design.
• Experience with ARM processor architecture and/or RISC-V ISA.
• Knowledge of CPU pipelines, instruction decoding, execution units, caches, and memory hierarchy.
• Understanding of performance, power, and area (PPA) trade-offs in CPU design.
• Experience with RTL simulation, debugging, and synthesis-aware coding practices.
• Strong problem-solving skills and ability to work on complex CPU design challenges.

Preferred Expertise

• Experience with ARM or RISC-V CPU core development.
• Knowledge of out-of-order or in-order processor architectures.
• Exposure to formal verification, lint, CDC, and RTL quality checks.
• Familiarity with CPU performance optimization and microarchitectural trade-offs.