RTL Design Lead

L&T Technology Services; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

L&T Technology Services in Bengaluru seeks a senior RTL engineer to join our growing ASIC team. You will lead design, synthesis, STA and FV efforts and work closely with verification teams to ensure silicon readiness.

Ideal candidates have 8+ years of ASIC RTL experience, strong Verilog/SystemVerilog skills, and hands-on knowledge of AMBA protocols and multi-clock domain designs. Collaboration across teams is essential for timely delivery.

Qualifications

• 8+ years in ASIC RTL Design, Synthesis, STA & FV.
• Experience in Logic design/micro-architecture/RTL coding.
• Hands on with multi clock domain blocks integration.
• Verilog/System-Verilog proficiency.
• Knowledge of AMBA AXI, AHB, APB, clocking/reset/debug architecture.
• Multi Clock designs and asynchronous interfaces experience.
• Familiar with Lint, CDC, Design Compiler and PrimeTime.
• Collaborate with DV/validation teams for pre/post-Silicon debug.
• Low power design experience preferred.
• Synthesis and timing concepts understanding.

Responsibilities

• Lead RTL design, synthesis, and timing closure for ASIC blocks.
• Collaborate with verification and validation teams for silicon readiness.
• Drive multi clock domain integration and interface design.
• Ensure low power design considerations are applied where relevant.
• Mentor junior engineers and contribute to RTL coding standards.

Skills

ASIC RTL Design

Synthesis

STA

FV

Logic design

RTL coding

Multi clock domain

Verilog/SystemVerilog

AMBA AXI/AHB/APB

Asynchronous interface

Low power design

Timing concepts

Tools

Design Compiler

PrimeTime

Lint

CDC

Job description

Below is the JD for RTL engineers. We need to build strong RTL team.

• Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV
• Experience in Logic design/micro-architecture/RTL coding is a must.
• Must have hands on experience with design and integration of complex multi clock domain blocks
• Experience in Verilog/System-Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
• Work closely with the Design verification and validation teams for pre/post Silicon debug
• Hands on experience in Low power design is preferable
• Experience in Synthesis / Understanding of timing concepts for ASIC is must