Senior/Lead Digital Design Engineer

Incise Infotech; Pune District, Bengaluru; On-site; INR 400,000 - 700,000; Full time

Job summary

Incise Infotech in Pune invites an experienced Senior RTL Design Engineer to join our ASIC/SoC team. You will contribute hands-on RTL coding in Verilog/SystemVerilog and help drive design quality, timing, and integration across globally distributed teams.

The ideal candidate has 7+ years in digital logic design, strong control-path and data-path knowledge, and familiarity with DV requirements, test plans, and coverage metrics.

Qualifications

• 7+ years of experience in digital logic design and RTL development.
• Strong hands-on experience with Verilog and SystemVerilog.
• Strong understanding of control-path and data-path design concepts.
• Experience with RTL design methodologies and correct-by-construction design principles.
• Experience defining DV requirements, test plans, and coverage metrics.
• Knowledge of: Lint, CDC, Formal Equivalence, DFT concepts, Power analysis, Logic Synthesis, STA, Timing constraints.

Responsibilities

• Develop RTL in Verilog/SystemVerilog for ASIC/SoC.
• Define DV requirements, test plans, and coverage metrics.
• Collaborate with globally distributed teams to ensure design quality.

Skills

RTL design

Digital logic

Debugging

Team collaboration

Problem solving

Communication

Control-path and data-path design

Timing/synthesis/STA

Tools

Verilog

SystemVerilog

Linter

CDC

Formal Equivalence

DFT

Power analysis

Logic Synthesis

STA

Timing constraints

Job description

We are looking for an experienced Senior RTL Design Engineer with 7+ years of experience in digital logic design and hands-on RTL coding using Verilog/SystemVerilog. The ideal candidate should have strong expertise in digital design, RTL development, design quality, timing, and ASIC/SoC development.

Required Skills

• 7+ years of experience in digital logic design and RTL development.
• Strong hands-on experience with Verilog and SystemVerilog.
• Strong understanding of control-path and data-path design concepts.
• Experience with RTL design methodologies and correct-by-construction design principles.
• Experience defining DV requirements, test plans, and coverage metrics.
• Knowledge of:
• Lint
• CDC
• Formal Equivalence
• DFT concepts
• Power analysis
• Logic Synthesis
• Static Timing Analysis (STA)
• Timing constraints
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and teamwork skills with the ability to work with globally distributed teams.

Good to Have

• Experience with standard on-chip protocols such as APB, AHB, AXI, and AXI-Stream.
• Knowledge of Processor/SoC architecture.
• Understanding of DSP fundamentals.
• Experience with complete ASIC/SoC product development and productization.
• Exposure to front-end RTL-to-GDSII design flow is an added advantage.