RTL Design Engineer : Bangalore

Incise Infotech; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Incise Infotech is seeking an experienced ASIC/SoC Design Engineer to work on RTL design for complex SoCs. You will participate in multi-clock designs, asynchronous interfaces, and integration of IP blocks within a robust SoC development flow.

The role requires hands-on experience with Verilog/SystemVerilog, AMBA protocols (AXI, AHB, APB), and strong debugging skills to resolve RTL and integration issues. You will collaborate across cross-functional teams to meet timing, lint, and CDC

Qualifications

• Experience in logic design and RTL coding for complex SoCs.
• Hands-on SoC design and integration for multi‑clock systems.
• Proficiency in Verilog/SystemVerilog and AMBA protocols (AXI/AHB/APB).
• Knowledge of synthesis, timing concepts, CDC/Lint, ECO fixes, and formal verification.

Responsibilities

• Design and implement RTL for ASIC/SoC projects.
• Integrate IP blocks within complex SoCs and debug integration issues.
• Collaborate with cross-functional teams to meet timing and area goals.
• Apply ASIC development methodologies, including CDC and lint checks.
• Support ECO fixes and maintain verification coverage.

Skills

Logic design

RTL coding

SoC design

Verilog/SystemVerilog

Multi-clock designs

Asynchronous interfaces

AMBA protocols

Clocking & reset architecture

RTL debugging

ECO fixes

Formal verification

Job description

We are looking for an experienced ASIC/SoC Design Engineer with strong expertise in RTL design and complex SoC development. The ideal candidate should have hands‑on experience in logic design, RTL coding, multi-clock designs, asynchronous interfaces, and ASIC development methodologies.

Key Responsibilities & Requirements:

• Strong experience in Logic Design and RTL Coding.
• Hands‑on experience in SoC Design and Integration for complex SoCs.
• Proficiency in Verilog/SystemVerilog.
• Strong understanding of Multi-Clock Designs and Asynchronous Interfaces.
• Experience with ASIC development tools and methodologies, including Lint and CDC.
• Knowledge of Synthesis and Timing Concepts is an added advantage.
• Experience in ECO Fixes and Formal Verification.
• Good understanding of AMBA protocols, including AXI, AHB, and APB.
• Strong knowledge of SoC Clocking and Reset Architecture.
• Ability to debug complex RTL and integration issues and collaborate effectively with cross‑functional teams.