RTL Design Lead

Erbity; Ahmedabad District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity is seeking an experienced RTL Design Lead to drive RTL development for complex ASIC/SoC projects in Ahmedabad. You will craft high-quality RTL using Verilog/SystemVerilog and collaborate with architecture, verification, DFT, and physical design teams to ensure timely delivery.

You will mentor junior engineers, lead block-level design activities, and oversee synthesis, lint, CDC, and power design methodologies, while refining micro-architecture with architecture and verification teams.

Qualifications

• Strong experience in RTL Design for ASIC/SoC projects.
• Hands-on expertise in Verilog/SystemVerilog.
• Good understanding of AMBA protocols (AXI/AHB/APB).
• Experience with synthesis, lint, CDC, and low-power design methodologies.
• Strong debugging and problem-solving skills.
• Prior team handling or technical leadership experience is preferred.

Responsibilities

• Lead RTL design activities for complex ASIC/SoC development projects
• Work closely with architecture and verification teams to define micro-architecture and implementation strategies
• Develop high-quality RTL using Verilog/SystemVerilog
• Drive block-level design, integration, lint, CDC, and synthesis activities
• Ensure design quality and timely project execution
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages
• Collaborate with cross-functional teams including DFT, Physical Design, and Verification
• Mentor junior engineers and support technical reviews

Skills

RTL Design

Verilog/SystemVerilog

AMBA protocols

Synthesis & CDC

Debugging

Leadership

Job description

Job Description

• Lead RTL design activities for complex ASIC/SoC development projects
• Work closely with architecture and verification teams to define micro-architecture and implementation strategies
• Develop high-quality RTL using Verilog/SystemVerilog
• Drive block-level design, integration, lint, CDC, and synthesis activities
• Ensure design quality and timely project execution
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages
• Collaborate with cross-functional teams including DFT, Physical Design, and Verification
• Mentor junior engineers and support technical reviews

Required Skills

• Strong experience in RTL Design for ASIC/SoC projects
• Hands-on expertise in Verilog/SystemVerilog
• Good understanding of AMBA protocols (AXI/AHB/APB)
• Experience with synthesis, lint, CDC, and low-power design methodologies
• Strong debugging and problem-solving skills
• Prior team handling or technical leadership experience is preferred