RTL Design Lead

MediaTek; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

MediaTek in Bengaluru is seeking a Design Lead to guide RTL design and SoC development. You will coordinate hardware teams, drive microarchitecture definitions, and balance power, performance, area, and schedule from concept to tape-out.

You will mentor engineers, oversee verification, timing, and sign-off, and collaborate with architecture and physical design to meet aggressive targets.

Qualifications

• 7 to 15 years of RTL design experience.
• Bachelor's or Master's in Electrical, Electronics, or Computer Engineering.
• Proven track record of technical leadership and management capacity.

Responsibilities

• Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.
• Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Partner with architecture, verification, and physical design teams.
• Drive resolution on complex bugs, logic issues, and sign-off checks.

Skills

RTL design

Verilog

SystemVerilog

Python

Perl

Technical leadership

ARM architecture

RISC-V architecture

PCIe

DDR

Education

Bachelor's or Master's in Electrical, Electronics or Computer Engineering

Job description

Design Lead works with hardware engineering teams to build complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks.

Guides microarchitecture definition, RTL design, verification, and physical implementation from conception through tape-out, balancing power, performance, area, and schedule goals.

Key Responsibilities

• Execution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.
• Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams.
• Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.

Requirements & Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 7 to 15 years of relevant RTL design experience.
• Proven track record of technical leadership and management capacity.

Core Technical Skills

• Design Languages: Advanced proficiency in Verilog, System-Verilog, and scripting tools like Python or Perl.
• Architecture Knowledge: Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR).
• Sign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).