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Tessolve is seeking an experienced RTL design engineer to translate architectures into robust Verilog/SystemVerilog RTL blocks for ASIC/SoC projects in Bengaluru. You will work closely with verification and physical design teams to ensure timing, power, and area targets are met.
The role requires strong HDL proficiency, a solid understanding of digital design fundamentals, and hands-on experience with AMBA protocols (AXI/AHB/APB). Prior ASIC/SoC design exposure is essential.