RTL Design Engineer Role

HCLTech; Bengaluru Urban; On-site; INR 2,500,000 - 5,000,000; Full time

Job summary

HCLTech is seeking an RTL Design Engineer in Bengaluru, India, with 5-12 years of ASIC/SoC experience to drive development from architecture to implementation. The role requires strong RTL design using Verilog/SystemVerilog or VHDL, ASIC/SoC experience, and the ability to collaborate across Design, Verification, and Synthesis teams.

Good-to-have exposure to UVM-based verification and scripting in Python/Perl/Shell. Bachelor’s or Master’s in EE/EC/related field required.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Proficiency in RTL design using Verilog/SystemVerilog or VHDL is required.
• Experience in ASIC/SoC development and functional verification with RTL debugging.
• Familiarity with timing analysis, timing closure, and SDC constraints; ability to work with cross-functional teams.

Responsibilities

• Drive development of high-performance digital designs from architecture to implementation.
• Develop RTL in Verilog/SystemVerilog or VHDL and perform RTL debugging.
• Coordinate with Design, Verification and Synthesis teams throughout the development cycle.
• Analyze timing constraints and ensure design meets SDC requirements.

Skills

RTL design

Verilog/SystemVerilog

VHDL

ASIC/SoC development

Functional verification

Timing analysis

SDC constraints

Collaboration across teams

Education

Bachelor's or Master's degree in Electrical Engineering / Electronics / Computer Engineering

Tools

Python scripting

Perl scripting

Shell scripting

Job description

RTL Design Engineer | 5-12 Years

We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.

Key Requirements:

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

Good to Have:

• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows

Qualification:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies
• Collaborative and fast-paced engineering environment
• Strong learning and career growth opportunities
• Competitive compensation and benefits package