RTL Design Engineer

HCLTech; Bengaluru Urban; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

HCLTech is seeking an RTL Design Engineer with 5-10 years of experience for ASIC/SoC development. The role focuses on designing, coding, and validating complex digital designs while collaborating with cross-functional teams to deliver high-quality silicon solutions.

The candidate will develop RTL using Verilog/SystemVerilog or VHDL, perform functional verification, and support timing analysis and constraint development.

Qualifications

• 5–10 years hands-on RTL design experience in ASIC/SoC.
• Strong proficiency in Verilog/SystemVerilog or VHDL.
• Bachelor's or Master's degree in E.E., Electronics or Computer Engineering.
• Understanding of timing analysis and SDC constraints.

Responsibilities

• Develop RTL designs using Verilog/SystemVerilog or VHDL.
• Perform functional verification and debugging via simulation and formal methods.
• Participate in design reviews; ensure RTL coding standards.
• Support timing analysis, timing closure, and constraint development (SDC).
• Collaborate with Verification, Synthesis, Physical Design and Architecture teams.
• Analyze and resolve design, functionality, and timing issues.
• Contribute to SoC/ASIC integration and tape-out activities.

Skills

Verilog/SystemVerilog

VHDL

RTL design

Digital design fundamentals

SDC constraints

UVM-based verification

Python/Perl/Shell scripting

EDA tools

Education

Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering

Tools

EDA tools

Job description

RTL Design Engineer | 5-10 Years Experience

Job Summary

We are looking for a skilled RTL Design Engineer with 5-10 years of experience in ASIC/SoC development. The ideal candidate will be responsible for designing, coding, and validating complex digital designs, working closely with cross-functional teams to deliver high-quality silicon solutions.

Key Responsibilities

• Develop and maintain RTL designs using Verilog/SystemVerilog or VHDL.
• Perform functional verification and debugging of digital designs through simulation and formal verification techniques.
• Participate in design reviews and ensure compliance with RTL coding standards and best practices.
• Support timing analysis, timing closure, and constraint development using SDC.
• Collaborate with Verification, Synthesis, Physical Design, and Architecture teams throughout the design lifecycle.
• Analyze and resolve design, functionality, and timing-related issues.
• Contribute to successful SoC/ASIC integration and tape-out activities.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 5-10 years of hands-on RTL design experience in ASIC/SoC development.
• Strong proficiency in Verilog/SystemVerilog or VHDL.
• Solid understanding of digital design fundamentals, including:
• Combinational and Sequential Logic
• Finite State Machines (FSMs)
• Timing Analysis and Clocking Concepts
• Experience with RTL verification and debugging.
• Knowledge of SDC constraints and timing closure methodologies.
• Strong analytical, problem-solving, and debugging skills.
• Excellent communication and teamwork abilities.

Preferred Skills

• Exposure to UVM-based verification environments.
• Experience with synthesis, STA, and ASIC design flows.
• Scripting knowledge in Python, Perl, or Shell.
• Experience with industry-standard EDA tools.

Why Join Us?

• Opportunity to work on advanced ASIC/SoC technologies.
• Collaborative and innovation-driven engineering environment.
• Strong career growth and learning opportunities.
• Competitive compensation and benefits package.