Digital Design Engineer

Texas Instruments; India; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

Texas Instruments is seeking an RTL Digital Design Engineer with 3–5 years of hands-on experience in digital design for ASICs or SoCs. You will contribute from specification to tape-out, working with architecture, verification, and physical design teams.

Responsibilities include RTL coding, microarchitecture, and collaboration across cross-functional teams to ensure efficient design implementation, timing closure, and quality.

Qualifications

• Proficient in RTL coding and digital design for ASICs/SoCs.
• Experience with Verilog, VHDL, and SystemVerilog.

Responsibilities

• RTL coding and microarchitecture development.
• Collaborate with system architects and cross‑functional teams for design/verification.
• Optimize designs for performance, area, and power targets.
• Coordinate with verification and physical design teams for timing closure and constraints.

Skills

RTL Design

Verilog

VHDL

SystemVerilog

ASIC/SoC

Job description

Job Title: RTL Digital Design Engineer

We are looking for a passionate RTL Design Engineer with 3–5 years of hands‑on experience in digital design for ASICs or SoCs. The candidate will work on cutting‑edge semiconductor designs from specification to tape‑out, collaborating with cross‑functional teams including architecture, verification, and physical design.

Key Responsibilities:

• RTL Coding and microarchitecture:
• Design and implementation of digital logic at the RTL level using Verilog, VHDL, System verilog.
• Collaborate with system architects and other cross functional teams to ensure efficient design implementation and its verification.
• Optimize designs for performance, area, and power targets
• Contribute to system architecture.
• Problem Solving and Quality:
• Participate in pre‑silicon and post‑silicon debug.
• Contribute to design reviews and improvements.
• Work closely with verification engineers to define test plans.
• Coordinate with physical design teams for timing closure and synthesis constraints.