RTL Design Engineer

ACL Digital; Hyderabad; On-site; INR 600,000 - 1,000,000; Full time

Job summary

A leading semiconductor company in Hyderabad is seeking a motivated RTL Design Engineer to develop and verify digital logic using Verilog/SystemVerilog. The ideal candidate will have a Bachelor's or Master's degree in engineering and 2-3 years of experience, collaborating with teams to achieve project objectives.

Qualifications

• 2-3 years of relevant experience in RTL design.
• Strong understanding of ASIC flow and verification processes.

Responsibilities

• Develop, integrate, and verify digital logic.
• Collaborate with cross-functional teams to achieve tapeout goals.
• Support gate-level simulations and implement ECOs.

Skills

Verilog/SystemVerilog

Digital design fundamentals

ASIC/SoC IP integration

Debugging simulation failures

Timing closure

Education

Bachelor's or Master's degree in engineering

Job description

Overview

Job Title: RTL Design Engineers

Job Description:

• Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog.
• Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams.
• Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow.
• You'll debug simulation failures, implement ECOs, and support gate-level simulations.
• Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.
• Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.

Share resumes to [e-mail]

Seniority level

• Associate

Employment type

• Full-time

Job function

• Industries

Industries

• Semiconductor Manufacturing

Referrals increase your chances of interviewing at ACL Digital by 2x