RTL Design Engineer Role

HCLTech; Bengaluru; On-site; INR 1,300,000 - 1,700,000; Full time

Benefits offered by this job

Health insurance

Job summary

HCLTech is seeking an RTL Design Engineer with 5-12 years of ASIC/SoC experience to drive high-performance digital designs from architecture to implementation.

Qualified candidates will have strong RTL design skills (Verilog/SystemVerilog or VHDL), hands-on ASIC/SoC development, and experience in verification, timing analysis, and debugging within a collaborative team.

Qualifications

• Experience in RTL design with Verilog/SystemVerilog or VHDL.
• Hands-on ASIC/SoC development experience.
• Strong understanding of digital design concepts including combinational, sequential logic and FSMs.
• Experience in functional verification and RTL debugging.
• Knowledge of timing analysis, timing closure, and SDC constraints; Lint/CDC.

Responsibilities

• Drive development of high-performance digital designs from architecture to implementation.
• Collaborate with Design, Verification and Synthesis teams across the development cycle.
• Support timing analysis and debugging throughout the RTL flow.
• Contribute to RTL linting and CDC verification as part of the verification effort.

Skills

RTL design

Verilog/SystemVerilog

VHDL

ASIC/SoC development

Digital design concepts

Functional verification

RTL debugging

Timing analysis

SDC constraints

Lint/CDC

Team collaboration

Education

Bachelor's or Master's in Electrical Engineering, Electronics, Computer Engineering, or related field

Tools

UVM

Python scripting

Shell scripting

Job description

RTL Design Engineer | 5-12 Years

We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.

Key Requirements:

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

Good to Have:

• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows

Qualification:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies
• Collaborative and fast-paced engineering environment
• Strong learning and career growth opportunities
• Competitive compensation and benefits package