RTL Design Engineer Role

HCLTech; Bengaluru; On-site; INR 1,400,000 - 2,300,000; Full time

Job summary

HCLTech is seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive high-performance digital designs from architecture to implementation.

The role requires strong RTL design skills (Verilog/SystemVerilog or VHDL), hands-on ASIC/SoC development, and solid knowledge of timing analysis, SDC constraints, and debugging. Collaboration with Design, Verification, and Synthesis teams is essential for success.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Strong experience in RTL design using Verilog/SystemVerilog or VHDL.
• Hands-on experience in ASIC/SoC development.
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs.
• Experience in functional verification and RTL debugging.
• Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.

Skills

RTL design

Verilog

SystemVerilog

VHDL

ASIC/SoC development

Digital design concepts

FSMs

Functional verification

RTL debugging

Timing analysis

Timing closure

SDC constraints

Lint/CDC

UVM

Python

Perl

Shell scripting

STA

Synthesis flows

Education

Electrical Engineering

Electronics

Computer Engineering

Job description

We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.

Key Requirements:

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

Good to Have:

• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows

Qualification:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies
• Collaborative and fast-paced engineering environment
• Strong learning and career growth opportunities
• Competitive compensation and benefits package