RTL Design Engineer- Immediate Opportunity

Tata Elxsi, Inc.; Bengaluru; Sur place; INR 1 200 000 - 2 400 000; Plein temps

Résumé du poste

Tata Elxsi, Inc. is seeking an experienced RTL Design Engineer to develop high-quality RTL for ASIC/FPGA products. You will work with verification and physical design teams to ensure robust micro-architecture and integration readiness.

The role involves linting, CDC/RDC checks, and synthesis readiness, plus collaboration on design reviews and documentation to support silicon bring-up and FPGA prototyping.

Qualifications

• Experience in RTL design for ASIC/FPGA-based products.
• Proficient in Verilog/SystemVerilog and RTL implementation.
• Experience with RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Experience supporting SoC/IP integration and FPGA prototyping.
• Experience collaborating with verification teams to resolve design issues.
• Ability to prepare design documentation.

Responsabilités

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off.
• Support FPGA prototyping and silicon bring-up activities as required.
• Prepare and maintain design documentation.

Connaissances

RTL design

Verilog

SystemVerilog

ASIC/FPGA

micro-architecture

digital IPs

SoC integration

linting

CDC/RDC analysis

synthesis readiness

design reviews

documentation

Outils

Linting tools

Synthesis tools

Verif. collaboration

Description du poste

Experience - 3 to 6yrs

Location- Bangalore only

We are seeking an experienced RTL Design Engineer with strong expertise in digital IC design, micro-architecture development, and RTL implementation for ASIC/FPGA-based products. The candidate will be responsible for developing high-quality RTL designs, supporting integration activities, and working closely with verification and physical design teams.

Key Responsibilities

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/ System Verilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off.
• Support FPGA prototyping and silicon bring-up activities as required.
• Prepare and maintain design documentation.