RTL Design Engineer - 2326

Sunrise Biztech Systems; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Bengaluru is seeking an experienced RTL Design Engineer with 10+ years of hands-on ASIC verification expertise.

The role focuses on owning IP and top-level verification for SerDes subsystems, interfacing digital RTL with analog models, and ensuring robust system-level coverage. You will collaborate with RTL, analog, and firmware teams, build and upgrade UVM testbenches, and drive test planning to achieve coverage closure.

Qualifications

• Must have 10+ years of RTL design/verification experience in semiconductor/ASIC domains.
• Proficient with Verilog, SystemVerilog and UVM testbench concepts.
• Strong experience with IP-level TB development and EDA tools (Verdi, VCS).

Responsibilities

• Own IP and top-level ASIC verification for SerDes subsystems.
• Verify digital RTL with analog behavioral models using SystemVerilog/UVM.
• Collaborate across RTL, analog and firmware teams to ensure system-level interfaces.
• Develop testbenches and drive coverage to closure.
• Utilize automation and AI tools to accelerate debugging.

Skills

Verilog

SystemVerilog

UVM

Tools

Verdi

VCS

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: RTL Design Engineer

Experience: 10+ Years

Location: Bengaluru

Contract tenure: 1 year

Top 3 mandatory (primary) skills:

• Verilog, system verilog, UVM


• IP level TB component development


• Mastery in EDA tools (Verdi,vcs) etc

Good to have (secondary) skills:

• Comfortable in scripting for automation


• AI tools usage


• Experience in digital+analog verification
  

Job Description

• Owns IP and top-level ASIC verification for complex SerDes subsystems.


• Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.


• Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.


• Metrics: Drives testbench architecture and test planning to achieve coverage closure.
  

Job Responsibilities / Day-to-Day Activities

• Spec Review: Analyze design specs and collaborate with designers to align test plans.


• Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.


• Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.


• Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.


• Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.