RTL Design Engineer- Lead

Einfochips; Bengaluru, Dadri; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Einfochips is seeking experienced professionals in Bengaluru for roles focused on RTL Design, ASIC, and SoC Development. Candidates should have 10-15 years of experience with hands-on expertise in Verilog, SystemVerilog, and VHDL. The successful applicant will lead design teams, manage projects end-to-end, and possess excellent communication and stakeholder management skills. This is an excellent opportunity to leverage your technical skills while leading complex design aspects in a dynamic environment.

Qualifications

• 10-15 years of experience in RTL Design, ASIC, and SoC Design.
• Strong hands-on expertise in Verilog, SystemVerilog, and VHDL.
• Experience in micro-architecture development and timing closure.

Responsibilities

• Lead design teams and drive end-to-end project execution.
• Integrate designs and ensure compliance with protocols.
• Problem solving and debugging in design flow.

Skills

RTL Design

ASIC Design

SoC Design

Verilog

SystemVerilog

VHDL

Micro-architecture Development

Debugging

Communication Skills

Job description

Overview

Location: Bangalore / Noida

Experience: 10-15 Years

Notice Period: Open to all notice periods

Job Description

Strong experience in RTL Design / ASIC / SoC Design

Hands-on expertise in Verilog / SystemVerilog / VHDL

Experience in micro-architecture development, RTL coding, and design integration

Strong understanding of SoC architecture and industry-standard protocols such as AXI, AHB, APB, PCIe, USB, etc.

Experience in timing closure, synthesis, and low-power design concepts

Ability to lead design teams and drive end-to-end project execution

Strong debugging and problem-solving skills

Excellent stakeholder management and communication skills