RTL Design Engineer

Tata Elxsi; Hyderabad, Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Tata Elxsi, Inc. is seeking a skilled RTL engineer in Hyderabad to design and implement digital IPs and subsystems, using Verilog/SystemVerilog. The role involves RTL quality checks, synthesis readiness, and collaboration with verification teams to ensure a clean sign-off for ASIC/FPGA projects.

The ideal candidate will have strong digital design fundamentals, experience with timing analysis, CDC tools, and the ability to support silicon bring-up and FPGA prototyping as required.

Qualifications

• Strong proficiency in Verilog/SystemVerilog RTL coding and digital design concepts.
• Experience with ASIC/FPGA design and development flows.
• Familiarity with synthesis, timing analysis, lint, and CDC tools.

Responsibilities

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off; assist FPGA prototyping and silicon bring-up as needed.
• Prepare and maintain design documentation.

Skills

Verilog/SystemVerilog RTL coding

Digital design fundamentals

ASIC/FPGA design flows

Synthesis and timing analysis

Debugging and problem-solving

Job description

Tata Elxsi works with leading OEMs and suppliers in the automotive & transportation industries for R&D, Design and Product Engineering Services, right from architecture to launch and beyond. We bring together technologies that accelerate development & testing of connected autonomous and electric cars & off-highway vehicles.

Key Responsibilities:

• Analyze specifications and develop micro-architecture for digital IPs and subsystems.
• Design and implement RTL using Verilog/ System Verilog.
• Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
• Support SoC/IP integration activities.
• Participate in design reviews and technical discussions.
• Collaborate with verification teams to resolve design issues and achieve quality sign-off.Support FPGA prototyping and silicon bring-up activities as required.
• Prepare and maintain design documentation.

Required Skills:

• Strong proficiency in Verilog/SystemVerilog RTL coding.
• Good understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts.
• Experience in ASIC/FPGA design and development flows.
• Knowledge of synthesis, timing analysis, lint, and CDC tools.
• Strong debugging and problem-solving skills.