ASIC RTL Design Engineer

Sevya Multimedia; Hyderabad; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Sevya Multimedia in Hyderabad, India is seeking experienced engineers to work on cutting edge technology with complex functionality, focusing on RTL design and SoC integration.

Ideal candidates will have hands-on RTL experience for IP and ASIC subsystems, plus strong knowledge of clocks, resets, memory maps, and hierarchical bus interconnects, with proficiency in EDA tools and Unix/Linux scripting.

Qualifications

• Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration.
• Proven hands-on experience with RTL design for IP, the subsystem for ASIC.
• Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect.
• Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power).
• Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design).
• Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys).
• Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
• Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills.
• Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
• Solutions orientation; Quality driven; Execution minded.

Skills

RTL Design

SoC Integration

Architecture

DV

DFT

Physical Design

IP Design

Clocking

Memory Map

Bus Interconnect

Lint

CDC

Synthesis

Power

EDA Tools

Cadence

Mentor

Synopsys

Unix/Linux

Shell

Python

Communication

Problem Solving

Team Player

Quick Learner

Urgency

Quality Driven

Tools

Skills

Job description

We need experienced engineers to work on cutting edge technology and with complex functionality.

Skills:

• Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration.
• Proven hands-on experience with RTL design for IP, the subsystem for ASIC.
• Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect
• Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power).
• Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design)
• Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys)
• Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
• Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
• Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
• Solutions orientation; Quality driven; Execution minded