Senior/ Lead RTL

Capgemini Engineering; Chennai District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading engineering company is seeking a Lead/Senior RTL Engineer based in Sriperumbudur, Tamil Nadu. The role requires 8 to 12 years of experience in VLSI design, particularly in SOC integration and RTL coding. Candidates should be well-versed in SOC flows, including the use of tools like Spyglass-Lint and DC-Synthesis. Proficiency in VHDL, Verilog, and various scripting languages will be essential. This is a full-time position at a mid-senior level.

Qualifications

• 8 to 12 years of experience in VLSI design.
• Strong knowledge of SOC Integration and RTL coding.
• Familiarity with SoC flows and scripting languages.

Responsibilities

• Responsible for SOC integration and RTL coding tasks.
• Utilize tools such as Spyglass-Lint and DC-Synthesis.
• Collaborate in SoC flow management.

Skills

VHDL

Verilog

Micro-architecture

RTL coding

CDC

Lint

Synthesis

STA

IP development

SoC integration

VCLP

scripting - Perl

scripting - Python

scripting - Shell

scripting - Tcl

Tools

Spyglass-Lint

DC-Synthesis

Cadence tool flow

Job description

Hiring -VLSI Engineers at Capgemini Engineering

Role: Lead /Senior RTL Engineer

Experience: 8 to 12 Years

Job Description:

• Should be good in Integration of SOC & RTL coding.
• Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.
• Should be aware of scripting language.
• Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
• Should have good understanding of SoC flows.

Primary Skills

• VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl.

Secondary Skills

• Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.

Seniority level: Mid-Senior level

Employment type: Full-time

Sriperumbudur, Tamil Nadu, India