RTL Design Engineer

Cyient; Bengaluru; On-site; INR 3,800,000 - 6,800,000; Full time

Job summary

Cyient in Bengaluru seeks a Senior Principal Engineer to lead semiconductor design from architecture to silicon validation, delivering high-performance, low-power ICs. This role also involves mentoring teams and influencing technical direction.

The position requires cross-functional collaboration with architecture, design, verification, DFT, and packaging teams to push silicon technology while aligning with product strategies.

Qualifications

• Experience in semiconductor design and RTL development.
• Strong collaboration with cross-functional teams across architecture, design, and verification.
• Proven ability to set technical direction and mentor engineers.

Responsibilities

• Develop RTL designs using Verilog/SystemVerilog based on architecture specs.
• Define digital micro-architecture for SoC/IP blocks.
• Design and integrate modules including motor control, industrial interfaces, embedded controllers, DMA/interrupts, GPIO/timers/PWM, UART/SPI/I2C/CAN/Ethernet.
• Perform RTL coding, linting, CDC and quality checks.
• Analyze architecture specs and translate them into RTL implementations.
• Support functional verification teams during simulation and debugging.
• Collaborate with DFT teams for scan insertion and testability requirements.
• Work with Synthesis and Physical Design teams to close implementation issues.
• Participate in RTL reviews, design reviews, and code reviews.
• Prepare RTL documentation and design specifications.

Skills

Verilog/SystemVerilog

RTL design

SoC integration

DFT collaboration

Synthesis & PD coordination

Job description

• Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
• Define and implement digital micro-architecture for SoC/IP blocks.
• Design and integrate modules related to:
  • Motor Control Systems
  • Industrial Communication Interfaces
  • Embedded Controllers
  • DMA, Interrupt Controllers
  • GPIO, Timers, PWM Modules
  • UART, SPI, I2C, CAN, Ethernet Interfaces
• Perform RTL coding, linting, CDC and quality checks.
• Analyze architecture specifications and convert them into RTL implementation.
• Support functional verification teams during simulation and debug activities.
• Collaborate with DFT teams for scan insertion and testability requirements.
• Work with Synthesis and Physical Design teams to close implementation issues.
• Participate in RTL reviews, design reviews, and code reviews.
• Prepare RTL documentation and design specifications.

Roles and Responsibilities

A seasoned technical leader with deep expertise in semiconductor design and development, the Senior Principal Engineer plays a pivotal role in driving innovation across all phases of chip development — from architecture and RTL design to physical implementation, verification, and silicon validation. This role is responsible for setting technical direction on cutting-edge projects, influencing product roadmaps, and ensuring the successful delivery of high-performance, low-power, and cost-effective integrated circuits. Acting as a mentor and technical advisor, the Senior Principal Engineer collaborates with cross-functional teams across architecture, design, verification, DFT, and packaging to push the boundaries of silicon technology while aligning engineering execution with business and product strategies.