RTL Design Integration Lead (Chip Top-Level)

HCL Technologies Limited; Bengaluru; On-site; INR 5,000,000 - 7,000,000; Full time

Job summary

HCL Technologies Limited seeks an experienced RTL Design/Integration Lead (Chip Top-Level) to own SoC RTL integration for complex chips and align architecture, design, verification and physical teams for successful tape-out.

You will integrate multiple IPs/blocks, ensure clean connectivity and modular structure, and drive synthesis-ready, lint-clean, and CDC-clean RTL. Strong leadership and cross-team coordination are essential.

Qualifications

• 10+ years in RTL integration leading SoC top-level design.
• Experience integrating multiple IPs/subsystems into a tape-out ready RTL.
• Strong interconnect, reset/clock, and NoC architecture understanding.
• Ability to coordinate across architecture, DV, DFT, and PD teams.

Responsibilities

• Own and drive top-level RTL integration across complex chips.
• Define interfaces, protocols, and interconnect connectivity.
• Lead RTL quality checks: lint, CDC/RDC, basic synthesis checks.
• Mentor RTL integration engineers and manage schedules.

Skills

RTL integration

SoC

Synthesis

Lint tools

CDC tools

NoC

Team leadership

Emulation

Tools

SpyGlass

Questa Lint

Questa CDC

Design Compiler

Genus

Job description

We are Hiring: RTL Design/Integration Lead (Chip Top-Level).

Min 10+ years in RTL Integration Lead (Chip Top-Level).

Lead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tape out.

Own top-level RTL integration of SoC:

• Integrate multiple IPs, subsystems, and third-party blocks
• Ensure clean connectivity, hierarchy, and modular structure
• Deliver synthesis-ready, lint-clean, and CDC-clean RTL

Work closely with architecture teams to:

• Translate SoC architecture into RTL structure

Ensure correct implementation of:

• Interconnects (NoC / bus-based)
• Address maps
• Reset and clock architecture

Interface & Connectivity Management

Define and validate:

• IP interfaces and protocols (AXI, AHB, APB, etc.)
• Address decoding and interconnect connectivity
• Interface mismatches
• Integration conflicts across teams

Define and integrate:

• Clocking architecture (multiple clock domains)
• Reset strategies (global/local resets)

Ensure:

• Clean CDC/RDC implementation

Quality & Signoff Readiness

Drive RTL quality checks:

• Lint (SpyGlass, Lint tools)
• CDC/RDC analysis
• Basic synthesis checks

Ensure RTL is:

• DV-ready
• DFT-ready
• PD-friendly

Interface with:

• IP/RTL design teams
• DV teams (for testbench integration support)
• DFT teams (for scan/test readiness)
• PD/STA teams (for implementation alignment)
• Act as central integration point across all domains
• Integration bugs
• Boot-up and reset sequence issues
• Connectivity and functional mismatches
• Support system-level bring-up in simulation/emulation

• Lead and mentor RTL integration engineers
• Drive integration schedules, milestones, and reviews
• Act as owner of top-level RTL quality and readiness

Strong expertise in:

• SoC integration and architecture

Deep understanding of:

Experience with:

• Lint, CDC/RDC tools
• Synthesis awareness
• Lint: SpyGlass / Questa Lint
• CDC: SpyGlass CDC / Questa CDC
• Synthesis: Design Compiler / Genus (Basic Awareness)
• Version control: Git/Perforce
• Strong system-level thinking
• Excellent coordination across large teams
• Problem-solving and debugging mindset

Good to Have

Experience in:

• NoC-based SoC architectures
• Emulation/FPGA bring-up

Scripting:

• Python / TCL / Perl
• Clean, integration-ready RTL (lint/CDC clean)
• Smooth handoff to DV, DFT, and PD teams
• Minimal integration bugs at system level
• First-pass success in SoC bring-up

Interested Engineers ping me or send invitation to connect further.