Digital IC Design Engineer

Texas Instruments; India; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading semiconductor company in India is seeking an experienced RTL Digital Design Engineer with 3–5 years of hands-on experience. The role involves designing digital logic using Verilog, VHDL, and SystemVerilog, collaborating with various cross-functional teams, and optimizing designs for performance. This position offers an opportunity to work on cutting-edge semiconductor designs, from specification to tape-out, in a dynamic environment fostering innovation.

Qualifications

• 3–5 years of experience in digital design for ASICs or SoCs.
• Hands-on experience with RTL design methodologies.
• Knowledge of verification and physical design processes.

Responsibilities

• Design and implement digital logic at the RTL level.
• Collaborate with system architects and cross-functional teams.
• Optimize designs for performance, area, and power.

Skills

RTL Coding

Verilog

VHDL

SystemVerilog

Digital Logic Design

Job description

Job Title

RTL Digital Design Engineer

Experience

3–5 years

Overview

We are looking for a passionate RTL Design Engineer with 3–5 years of hands‑on experience in digital design for ASICs or SoCs. The candidate will work on cutting‑edge semiconductor designs from specification to tape‑out, collaborating with cross‑functional teams including architecture, verification, and physical design.

Key Responsibilities

• RTL Coding and microarchitecture: Design and implementation of digital logic at the RTL level using Verilog, VHDL, SystemVerilog.
• Collaborate with system architects and other cross‑functional teams to ensure efficient design implementation and its verification.
• Optimize designs for performance, area, and power targets.
• Contribute to system architecture.
• Participate in pre‑silicon and post‑silicon debug.
• Contribute to design reviews and improvements.
• Work closely with verification engineers to define test plans.
• Coordinate with physical design teams for timing closure and synthesis constraints.