PV Lead

Mirafra; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mirafra in Bengaluru seeks an experienced PV lead to drive full-chip physical verification sign-off for complex SoCs. You will own DRC, LVS, ERC checks, lead sign-off readiness, and mentor PV engineers while coordinating with Foundry/PDK teams and PD/DFT/CAD groups.

The role requires 10+ years of PV experience and a strong track record in debugging violations, developing robust PV flows, and ensuring timely tapeouts across multi-team environments.

Qualifications

• 10+ years of experience in physical verification for SoCs.
• BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent.

Responsibilities

• Lead full-chip PV sign-off activities.
• Own and drive DRC, LVS, ERC, and related PV checks.
• Lead PV closure from block level through full-chip sign-off.
• Analyze and debug complex DRC/LVS/ERC violations and drive to closure.
• Work closely with Physical Design teams to resolve PV issues.
• Coordinate with Foundry/PDK teams for rule interpretation and verification issues.
• Review and debug verification results from large, complex SoC designs.
• Drive PV schedules, milestones, issue tracking, and sign-off readiness.
• Develop and improve PV methodologies, flows, and automation.
• Support tapeout/sign-off activities and ensure quality of final verification results.
• Mentor and provide technical guidance to PV engineers.
• Collaborate with Physical Design, Custom Layout, CAD, STA, DFT, and other teams.
• Participate in methodology reviews and improve verification turnaround time.

Skills

Physical Verification

DRC

LVS

ERC

PV sign-off

Mentoring

Education

BTECH/ MTECH in Electrical/Electronics/CS or Equivalent

Job description

Experience (years): 10+ years

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

• Lead full-chip Physical Verification (PV) sign-off activities.
• Own and drive DRC, LVS, ERC, and related physical verification checks.
• Lead PV closure from block level through full-chip sign-off.
• Analyze and debug complex DRC/LVS/ERC violations and drive them to closure.
• Work closely with Physical Design teams to resolve physical verification issues.
• Coordinate with Foundry/PDK teams for rule interpretation and verification issues.
• Review and debug verification results from large, complex SoC designs.
• Drive PV schedules, milestones, issue tracking, and sign-off readiness.
• Develop and improve PV methodologies, flows, and automation.
• Support tapeout/sign-off activities and ensure quality of final verification results.
• Mentor and provide technical guidance to PV engineers.
• Collaborate with Physical Design, Custom Layout, CAD, STA, DFT, and other teams.
• Participate in methodology reviews and improve verification turnaround time.