Physical Verification (PV) Engineer

Nxtwavesemi; India; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Nxtwavesemi is seeking a motivated Physical Verification (PV) Engineer to join its semiconductor engineering team in India. You will contribute to physical verification and sign-off across IP/block, subsystem, and full-chip levels, ensuring layouts meet design rules, connectivity, reliability, and foundry requirements.

You will perform and analyze PV checks, debug violations, verify connectivity, and support parasitic extraction and verification flows.

Qualifications

• CMOS layout and PV concepts understanding.
• Experience with DRC, LVS, connectivity, and design rules.
• Knowledge of block-level and full-chip verification concepts.
• Strong debugging and problem-solving abilities.

Responsibilities

• Perform and analyze PV checks for blocks, IPs, subsystems, and full-chip designs.
• Debug DRC, LVS, ERC, antenna, density, and PV violations.
• Verify connectivity and physical implementation against design intent and source data.
• Support parasitic extraction and extraction-based verification flows.
• Analyze layout integration issues involving standard cells, memories, IPs, IOs, and hard macros.
• Support hierarchical and full-chip PV closure and sign-off readiness.

Skills

CMOS layout

PV concepts

DRC/LVS

Debugging skills

Block/full-chip verification

Education

BE/BTech/M.E./MTech (ECE/EE/CE/VLSI)

Tools

Scripting for PV automation

Job description

We are looking for a motivated Physical Verification (PV) Engineer to join our semiconductor engineering team. The candidate will contribute to physical verification and sign-off across IP/block, subsystem, and full-chip levels, ensuring that layouts meet design rules, connectivity, reliability, and foundry requirements.

What You'll Do

• Perform and analyze physical verification checks for blocks, IPs, subsystems, and full-chip designs.
• Debug DRC, LVS, ERC, antenna, density, and related physical verification violations.
• Verify connectivity and physical implementation against design intent and source data.
• Support parasitic extraction and extraction-based verification flows.
• Analyze layout integration issues involving standard cells, memories, analog IPs, IOs, and hard macros.
• Support hierarchical and full-chip physical verification closure.
• Work with layout, analog, digital, physical design, and foundry-facing teams to resolve issues.
• Support sign-off, tape-out readiness, methodology development, and verification automation.

Required Skills

• Good understanding of CMOS layout and physical verification concepts.
• Knowledge of DRC, LVS, connectivity, and physical design rules.
• Understanding of block-level and full-chip verification concepts.
• Good debugging, analytical, and problem-solving skills.

Good to Have

• PEX, ERC, antenna, density, reliability, and advanced-node verification.
• Analog/custom layout and mixed-signal physical verification.
• Hierarchical/full-chip sign-off and foundry deck understanding.
• Scripting and physical verification-flow automation.

Educational Qualification

B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, VLSI, Microelectronics, or a related field.

What We Look For

• Strong technical fundamentals and a practical engineering mindset.
• Ability to understand specifications and solve complex technical problems.
• Effective debugging, analysis, and communication skills.
• Ability to work independently and collaboratively across engineering teams.
• Curiosity and willingness to learn new semiconductor technologies and methodologies.

What You Will Work On

• IP/Block PV
• Subsystem PV
• Full-Chip PV
• DRC
• LVS
• ERC
• PEX
• Reliability
• Advanced Node Sign-Off
• Tape-Out

Closing Statement

Help ensure that physical designs are correct, manufacturable, and ready for semiconductor tape-out.