Design Verification Engineer

Cadence; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cadence is seeking a highly motivated verification engineer with expertise in functional verification and VIP development to contribute to cutting-edge technology in India. The role requires rapid adaptation to new protocols and strong communication with customers and internal teams.

Ideal candidates bring hands-on experience with SV/UVM, C/C++ scripting, and understanding of modern interfaces like UCIe, PCIe, CXL and Ethernet.

Qualifications

• BE/BTech/ME/MTech in Electrical/Electronics.
• 2–6 years of domain experience.
• Proficiency in functional verification and test environment creation using SV/UVM with strong debug skills.
• Hands-on knowledge of C/C++/Scripting.
• Experience with layered protocols such as UCIe, PCIe, CXL, Ethernet, Ualink.

Responsibilities

• Design, development, verification and deployment of the VIP.

Skills

SV/UVM

C/C++

Scripting

VIP development

UCIe/PCIe/CXL/Ethernet

Digital electronics

Programming fundamentals

Communication skills

Education

Electrical/Electronics degree (BE/BTech/ME/MTech)

Tools

Verilog/SystemVerilog

Job description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

About the Role

We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers.

Responsibilities

• Responsible for the design, development, verification and deployment of the VIP.

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Required Skills

• 2 to 6 years of domain experience
• Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills.
• Hands-on knowledge of C/C++/Scripting.
• Working experience on layered Protocols - UCIe, PCIe, CXL, Ethernet, Ualink.
• Prior VIP usage and development experience is a plus.
• Strong Digital Electronics and Programming fundamentals.
• Self-motivated individuals with strong analytical and communication skills.

Preferred Skills

• Demonstrate adaptability in a fast-paced environment, showing resilience in the face of challenges and maintaining a positive attitude.
• Exhibit a strong commitment to continuous learning and professional development, staying abreast of industry trends and technologies.
• Foster a collaborative team environment by being approachable and supportive.
• Display a proactive approach to problem-solving, taking initiative, and anticipating potential issues before they arise.