Lead NOC ASIC Design Verification

Cadence; Dadri; Presencial; INR 1 500 000 - 2 100 000; Tempo integral

Resumo da oferta

Cadence in India is seeking a Design Verification engineer for interconnect IP and Tensilica Processor subsystems. You will craft verification plans and drive coverage closure in a highly configurable design environment.

You will work closely with DV/Arch/Design/FW teams to deliver robust verification, build UVM-based environments, and apply AMBA AXI/AHB/APB protocols with SystemVerilog. Requirements include 4+ years in DV, strong communication, and hands-on experience with simulators such as

Qualificações

• 4+ years of design verification experience.
• Strong technical and interpersonal skills.
• Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
• Excellent knowledge and command over AMBA protocols like AXI, AHB and APB.
• Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches.
• Exposure to scripting languages like Perl, Unix shell or similar languages.
• Experience with development of fully automated flows.
• Experience with Gate Level Simulations.
• Excellent written and oral communication skills necessary.
• Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago etc.

Responsabilidades

• Design Verification for interconnect IP and Tensilica Processor subsystems.
• Craft verification plans and execute to verify highly complex configurable designs.
• Responsible for coverage collection and closure.
• Work with cross functional teams (DV/Arch/Design/FW) to identify coverage scope.
• Create/maintain UVM based DV environment.

Conhecimentos

Interconnects

NoCs

AMBA protocols

AXI

AHB

APB

SystemVerilog

UVM

Perl

Unix shell

automated flows

Gate Level Simulations

Cadence Xcelium

Indago

Ferramentas

Xcelium

Indago

Descrição da oferta de emprego

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

About the Role

Design Verification for interconnect IP and Tensilica Processor subsystems. Relevant experience in interconnect and subsystems is strongly preferred. Crafting verification plans and executing on those plans to verify highly complex and configurable designs. Responsible for coverage collection and closure. Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope. Responsible for creating / working with UVM based DV environment.

Responsibilities

• Design Verification for interconnect IP and Tensilica Processor subsystems.
• Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
• Responsible for coverage collection and closure.
• Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope.
• Responsible for creating / working with UVM based DV environment.

Qualifications

Required Skills

• 4+ years of design verification experience.
• Strong technical and interpersonal skills.
• Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
• Excellent knowledge and command over AMBA protocols like AXI, AHB and APB.
• Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches.
• Exposure to scripting languages like Perl, Unix shell or similar languages.
• Experience with development of fully automated flows.
• Experience with Gate Level Simulations.
• Excellent written and oral communication skills necessary.
• Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago etc.

Preferred Skills

• Understanding of Coherency concepts will be a plus.
• Experience with Formal Verification will be a plus.
• Experience with integrated verification flows for processors with C and SV language is a plus.