Design Engineer II

Cadence Design Systems; Dadri; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Cadence Design Systems is seeking to strengthen its verification capabilities in India. The role focuses on building high-quality verification infrastructure, including simulation testbenches and reusable UVM environments, while advancing formal verification and AI-driven coverage analysis.

The candidate will collaborate with microarchitecture, RTL design, and software teams to ensure verification plans align with ISA requirements, contributing to cutting-edge semiconductor design workflows.

Qualifications

• B.Tech/M.Tech in ECE with experience in SystemVerilog/UVM and C/C++ for architectural modeling.
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
• Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

Responsibilities

• Verification Infrastructure: Develop and lead simulation testbenches in C/C++/RTL and reusable UVM environments.
• Advanced Verification: Drive the integration of formal verification and AI-driven coverage analysis.
• Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Education

B.Tech/M.Tech in ECE

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview

Key Responsibilities:

• Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
• Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
• Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required Qualifications

• B.Tech/M.Tech in ECE with experience in SystemVerilog/UVM and C/C++ for architectural modeling.
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
• Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

We’re doing work that matters. Help us solve what others can’t.

Equality, Diversity, and Inclusion

Cadence is committed to equal employment opportunity throughout all levels of the organization.

Cadence is a proud equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

E-Verify

Cadence participates in the E-Verify program in certain U.S. locations as required by law.

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About Cadence

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiate the people of Cadence.