lead Design Engineer

Cadence; Bengaluru; On-site; INR 1,800,000 - 3,800,000; Full time

Job summary

Cadence in Bangalore, India is seeking a Lead Design Engineer – UCIe Verification to join our verification team. You will lead the verification of complex UCIe Controller IP, driving coverage-driven verification, protocol validation, and debug across collaborative cross-functional teams.

The ideal candidate brings 5+ years of hands-on verification experience, strong SystemVerilog/UVM skills, and a proven ability to translate complex specifications into robust verification scenarios that enable

Qualifications

• 5+ years of Design Verification experience with IP or subsystem verification.
• Strong hands-on ownership and debugging skills in SystemVerilog/UVM.
• Experience with verification methodology, test planning, and sign-off.

Responsibilities

• Verify complex UCIe Controller IP using SystemVerilog/UVM.
• Develop scalable verification environments and drive coverage closure.
• Collaborate with design, architecture, and validation teams to release high-quality IP.

Skills

SystemVerilog/UVM

Coverage-driven verification

Assertions / SVA

Debugging

Reusable testbenches

Education

BE/BTech/ME/MTech/MS in Electronics or Electrical or Computer Engineering

Tools

Cadence Xcelium

UVM testbench components

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description: Lead Design Engineer – UCIe Verification

Location

Bangalore, India

Function

Design Verification

Role

Lead Design Engineer – UCIe Controller Verification

Role Overview

We are looking for a highly motivated and technically strong Lead Design Engineer – Verification to join our UCIe verification team in Bangalore.

The candidate will contribute to the verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM, verification architecture, coverage-driven verification, protocol verification, and debug.

The engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.

Required Qualifications

• BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of relevant Design Verification experience, with strong hands-on ownership of IP or subsystem-level verification.
• Strong expertise in : SystemVerilogUVMConstrained-random verificationFunctional coverageCode coverageAssertions/SVARegression and failure debug
• Experience developing reusable UVM testbench components and verification infrastructure.
• Strong understanding of verification methodology, test planning, coverage closure, and sign-off.
• Experience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.
• Ability to analyze complex specifications and translate requirements into effective verification scenarios.
• Strong debugging and problem-solving skills.

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