Lead Design Engineer - Verification

Cadence Design Systems India Pvt Ltd; Bengaluru; Presencial; INR 4.000.000 - 6.000.000; Jornada completa

Descripción de la vacante

Cadence Design Systems India Pvt Ltd seeks a Lead Design Engineer – UCIe Verification in Bangalore. You will lead verification of complex UCIe Controller IP, building scalable environments and validating protocol scenarios. Strong SystemVerilog/UVM and coverage skills are required.

The role involves working with design, architecture and validation teams to drive coverage closure and high-quality IP releases for next-generation interconnect solutions.

Formación

• BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of relevant Design Verification experience with hands-on ownership of IP or subsystem verification.
• Strong expertise in SystemVerilog, UVM, constrained-random verification, coverage concepts and debug.

Responsabilidades

• Verify complex UCIe Controller IP and interconnect solutions.
• Develop scalable verification environments and testbenches.
• Drive coverage closure and debug failures to enable high-quality IP releases.
• Collaborate with design, architecture, validation and cross-functional teams.

Conocimientos

SystemVerilog

UVM

Constrained-random verification

Functional coverage

Code coverage

Assertions/SVA

Regression and failure debug

Reusable UVM testbench components

Verification methodology

Sign-off

Cadence Xcelium

Educación

BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or related

Herramientas

Cadence Xcelium

Descripción del empleo

Lead Design Engineer At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Lead Design Engineer – UCIe Verification

Location

Bangalore, India

Function

Design Verification

Role

Lead Design Engineer – UCIe Controller Verification

Role Overview

We are looking for a highly motivated and technically strong Lead Design Engineer – Verification to join our UCIe verification team in Bangalore. The candidate will contribute to the verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM, verification architecture, coverage-driven verification, protocol verification, and debug. The engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.

Required Qualifications

• BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of relevant Design Verification experience, with strong hands-on ownership of IP or subsystem-level verification.
• Strong expertise in:
  • SystemVerilog
  • UVM
  • Constrained-random verification
  • Functional coverage
  • Code coverage
  • Assertions/SVA
  • Regression and failure debug
  • Experience developing reusable UVM testbench components and verification infrastructure .
  • Strong understanding of verification methodology, test planning, coverage closure, and sign-off.
  • Experience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.
  • Ability to analyze complex specifications and translate requirements into effective verification scenarios.
  • Strong debugging and problem-solving skills.

Experience Level

Senior Level