Sr Principal Product Validation Engineer

Cadence Design Systems, Inc.; Dadri; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Cadence Design Systems in India seeks an experienced verification engineer with strong HDL and SystemVerilog skills to contribute to advanced SoC projects. You will work on functional verification environments, debug complex designs, and collaborate with cross-functional teams to ensure robust verification.

The role requires hands-on experience with Verilog/VHDL, SystemVerilog, UVM, and scripting for automation, plus knowledge of PCIe or USB protocols.

Qualifications

• Bachelors degree in Electrical/Electronics or Computer Science with strong HDL/verification background.
• Proficient in Verilog/VHDL and SystemVerilog/UVM.
• Experience with debugging complex digital designs and HVL.
• Familiarity with EDA tooling and scripting for automation.

Responsibilities

• Develop and maintain functional verification environments for SoCs.
• Debug and diagnose design/verification issues using HDL tools and EDA suites.
• Work with cross-functional teams to ensure robust verification coverage.

Skills

HDL languages (Verilog/VHDL)

SystemVerilog

UVM

C++

SoC verification

Functional verification

Scripting for automation

Education

Electrical/Electronics/CS Engineering degree

Tools

EDA tools (Cadence/others)

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
• Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
• Experience in process automation with scripting.
• Experience with SystemVerilog, C++, UVM.
• Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
• Experience designing and implementing complex functional verification environments is required.
• Knowledge of protocols like PCIe, USB3/4, DP an added advantage.

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