PMTS - Design Verification Engineer: SOC Focused

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Tsavorite Scalable Intelligence in Bengaluru seeks a Senior SoC Design Verification Engineer with 14+ years of experience to lead end-to-end DV on high-performance ARM-based SOCs. You will verify PCIe and CXL data paths, coordinate with RTL, architecture and firmware teams, and drive cross-IP verification in a chip-and-multi-chip context.

The role focuses on full-chip verification, real-silicon mindset, and scalable data movement across fabrics.

Qualifications

• Expertise in PCIe data-path verification and CXL interfaces.
• Strong SystemVerilog/UVM experience for DV.
• Experience with full-chip and multi-chip verification.

Responsibilities

• Validate PCIe/CXL data path at full chip and multichip level.
• Validate CXL data flows and Host–device coherency interactions.
• Execute SoC-level DV plan for flows pertaining to PCIe/CXL.
• Implement UVM-based system tests including mid-transaction reset and contention scenarios.
• Develop scoreboards and data integrity checks under high throughput and concurrent traffic.
• Capture waveforms and transaction traces for analysis.
• Coordinate firmware interaction and RTL/architecture collaboration.

Skills

PCIe protocol

CXL

SystemVerilog/UVM

Job description

SMTS -Design Verification Engineer: SOC Focused [Experience Level 14+]

Founded in 2023,by Industry veterans HQ in California,US

Company Description

We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Principal Design Verification Engineer: SOC Focused

Job Description

We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset verification.

Key Responsibilities

• Validate PCIe/CXL Data path at full chip and multichip level.
• Validate CXL data flows, Host–device coherency interactions
• Execute SoC-level DV plans for flows pertaining to PCIe / CXL
• Implement:
• UVM-based system tests including mid-transaction reset, contention scenario
• Scoreboards and data integrity checks under high throughput, concurrent traffic
• Waveforms
• Transaction traces
• Firmware interaction
• Collaborate with RTL, architecture, and firmware teams

Required Skills & Experience

• Strong knowledge of:
• PCIe protocol (transaction & data path focus)
• CXL (io/cache/mem)
• Proficiency in:
• SystemVerilog / UVM

Preferred Qualifications

• Multi-chip / chiplet system experience
• Exposure to real workloads (storage, networking, AI accelerators)