Senior Staff Engineer - Design Verification

TylSemi, Inc.; Karnataka; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

TYLsemi, Inc. is seeking a highly experienced Senior Staff Verification Engineer to lead the design verification of next‑generation high‑speed interconnect IPs and SoCs.

You will drive verification strategy, develop scalable UVM testbenches, and ensure protocol robustness across PCIe, CXL, Ethernet, and UCIe. The role demands deep SystemVerilog/UVM expertise, 12+ years in verification, and a track record of delivering high‑quality IP in fast‑paced environments.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 12+ years of Design Verification experience in complex SoC/IP verification.
• Proven experience defining verification architectures for high‑speed protocols.
• Strong expertise in SystemVerilog, UVM, coverage‑driven verification, and SVA.
• Hands‑on work with PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and related interfaces.
• Experience with UCIe PHY/Adapter layer verification is highly desirable.
• Deep understanding of SoC architecture and IP integration.

Responsibilities

• Define and implement scalable verification plans for PCIe, CXL, and Ethernet subsystems.
• Architect layered UVM agents, environments, and reusable components for protocol verification.
• Apply deep protocol knowledge to ensure compliance and robustness of IP/SoC.
• Drive functional coverage closure, assertion‑based verification, and metric‑driven sign‑off.
• Lead root‑cause analysis across simulation, emulation, and silicon bring‑up.
• Collaborate with design, architecture, and validation teams to deliver high‑quality verification.
• Mentor junior engineers and promote best practices in verification methodology.

Skills

PCIe

CXL

Ethernet

UCIe

SystemVerilog

UVM

C language

Education

Bachelor’s/Master’s in Electrical/Computer Engineering

Tools

SystemVerilog

UVM

SVA

Job description

About this position

AAbout TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are seeking a highly experienced Senior Staff Verification Engineer to lead the design verification of next‑generation high‑speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in PCIe, CXL, Ethernet, UCIe protocols, and advanced SystemVerilog, UVM methodologies, C and SV skills, driving verification strategy, execution, and innovation across complex projects.

WhatYou’llDo

• Verification Strategy : Define and implement scalable verification plans for PCIe, CXL, and Ethernet subsystems.
• UVM Testbench Development : Architect layered UVM agents, environments, and reusable components for protocol verification.
• Protocol Expertise : Apply in-depth knowledge of PCIe Gen5/Gen6, CXL 3.x, and Ethernet (200G/400G), UCIe PHY and Adaptor layer standards to ensure compliance and robustness.
• Coverage & Metrics : Drive functional coverage closure, assertion-based verification, and metric-driven sign-off.
• Debug & Analysis : Lead root‑cause analysis of complex issues across simulation, emulation, and silicon bring‑up.
• Collaboration : Partner with design, architecture, and validation teams to deliver high‑quality IP and SoC verification.
• Mentorship : Guide junior engineers, fostering best practices in verification methodology and protocol expertise.

What We’re Looking For

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in Design Verification, with strong exposure to complex SoC/IP verification
• Proven experience in defining and deploying verification architectures for high‑speed protocols
• Strong expertise in SystemVerilog, UVM, coverage-driven verification, and SVA
• Deep hands‑on experience with PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G or similar protocols
• Experience with UCIe PHY/Adapter layer verification is highly desirable
• Strong understanding of SoC architecture, high‑speed interfaces, and IP integration
• Excellent debugging, problem-solving, technical leadership, and mentoring skills

Good to Have

• Experience with AI/ML applications in verification workflows
• Exposure to emulation, prototyping, or hybrid verification platforms
• Familiarity with performance verification and power‑aware verification
• Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Experience building verification frameworks reused across multiple tape‑outs