Design Verification Lead

Mulya Technologies; Hyderabad; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

A technology startup is seeking a Design Verification Lead with extensive experience in PCIe/CXL based memory expansion. The candidate should possess strong skills in System Verilog and object-oriented programming with a background in verifying complex SoCs. Responsibilities include overseeing integration and verification projects, collaborating closely with RTL designers, and managing verification tasks. This role offers the opportunity to utilize advanced technical skills in a dynamic environment.

Qualifications

• 10+ years of experience or 6+ years with ME/MTech.
• Experience in verifying Fabric/Network on chips.
• Experience in bringing up testbenches for USB/PCIe/CXL.

Responsibilities

• Scope out integration and verification requirements with RTL designers.
• Close collaboration with SOC team for verification tasks.
• Verification of complex System IP features.

Skills

System Verilog

UVM

Object-Oriented Programming

USB/PCIe/CXL IP verification

Bus protocols AXI/AHB

Scripting languages (Perl, Python)

Analytical skills

Problem-solving skills

Education

BE/BTech in Electrical/Computer engineering

ME/MTech in Electrical/Computer engineering

Job description

Overview

TITLE: Design Verification Lead(PCIe/CXL based memory expander - Verification Engineer)

LOCATION: GREATER HYDERAD AREA

ABOUT COMPANY

Founded by highly respected Silicon Valley veterans, we are a startup headquartered in US with its design centre established in Santa Clara, California. / Hyderabad/ Bangalore

JOB DESCRIPTION

Minimum Qualifications

• BE/BTech in Electrical/Computer engineering with 10+ years of experience or ME/MTech in Electrical/Computer engineering with 6+ years of experience
• Should have hands on experience in System Verilog, UVM and Object-Oriented Programming
• Experience in verifying Fabric/Network on chips, Cache controller and Cache Coherency
• Proven track record in USB/PCIe/CXL IP verification both on FPGA and ASIC, with ability to bring up testbenches from scratch to defining test plan and sign-off for tape out.
• Integration and verification of complex System IP features.
• Work closely with RTL designers and SOC team to scope out integration and verification requirements.
• Good understanding of any memory protocol like DDR, ONFI, NAND, Flash SPI/QSPI.
• Proficiency in bus protocols AXI/AHB
• Proficiency in scripting languages like Perl, Python etc.
• Strong communication, collaboration, and interpersonal skills
• Strong analytical and problem-solving skills

Preferred Qualifications

• Experience in verification of PCIe/CXL based sub-system/SoC/IP.
• Knowledge of SoC with processor boot-flow.
• Knowledge of FPGA setup and running FPGA simulations.
• Experience in GLS is added advantage.
• Verification expertise in Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols.
• Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
• Analysing performance metrics of CXL/PCIe.
• System-level verification experience for PCIe/CXL.