Senior Design Verification Engineer

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

A leading semiconductor company in Bengaluru is looking for a Senior Design Verification Engineer to focus on validating end-to-end data-path for high-performance ARM-based SoCs. The ideal candidate should have experience in SoC verification, particularly around cache coherency and proficiency in SystemVerilog and UVM. This position involves collaboration with various teams to ensure high integrity and scalability of chip designs in complex configurations.

Qualifications

• Expertise in verifying ARM-based SoCs.
• Strong understanding of cache coherency structures.
• Proficiency with SystemVerilog and UVM.

Responsibilities

• Validate cache coherency across multiple cores and chips.
• Execute SoC-level DV plans focusing on cache coherency.
• Implement and verify mid-transaction reset tests.

Skills

Experience verifying ARM-based SoCs

Understanding of cache coherency (CHI / ACE preferred)

Proficiency in SystemVerilog / UVM

Solid grasp of DMA engines and memory systems

Job description

Senior Design Verification Engineer: SOC Focused [Experience Level 10+]

Job Description

We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset verification.

Key Responsibilities

Validate cache coherency across multiple cores, agents, accelerators, across chip boundaries

Execute SoC-level DV plans for flows pertaining Cache Coherency and involving ARM complexes in the flow path.

Implement system level stimulus for concurrent core/cache/dma/io traffic paths

Coherency across chip boundaries

Scalability testing:

N-chip configurations

Implement:

UVM-based system tests including mid-transaction reset, contention scenario

Scoreboards and data integrity checks under high throughput, concurrent traffic

Waveforms

Transaction traces

Firmware interaction

Collaborate with RTL, architecture, and firmware teams

Required Skills & Experience

Experience verifying ARM-based SoCs

Understanding of cache coherency (CHI / ACE preferred)

Proficiency in:

SystemVerilog / UVM

Solid grasp of:

DMA engines and memory systems

Preferred Qualifications

Multi-chip / chiplet system experience

Exposure to real workloads (storage, networking, AI accelerators)